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參數資料
| 型號： | LTC1623IS8 |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | MOSFETs |
| 英文描述： | 8-Bit, 40 kSPS ADC Serial Out, Low Power, Compatible to TLC540/545/1540, Single Ch. 8-SOIC |
| 中文描述： | 2 CHANNEL, BUF OR INV BASED MOSFET DRIVER, PDSO8 |
| 封裝： | 0.150 INCH, PLASTIC, SOP-8 |
| 文件頁數： | 8/12頁 |
| 文件大小： | 144K |
| 代理商： | LTC1623IS8 |
8
LTC 1623
Address
The LTC1623 has an address of 1011XXX; the four MSBs
are hard-wired, but the 3 LSBs are programmed by the
user with the help of two three-state address pins. Refer to
Table 1 for the pin configurations and their corresponding
addresses.
To conserve standby current, it is preferable to tie the
address pins to either V
CC
or GND. If more than four
addresses are needed, then either one of the address pins
can be tied to the third state of V
CC
/2 by using two equal
value resistors (
≤
1M) shown in Figure 2. Do not connect
both address pins to the V
CC
/2 state simultaneously
because this is not a valid address.
Charge Pump
To fully enhance the external N-channel switches, an
internal charge pump is used to boost the output gate drive
to a minimum of 2.7V and a maximum of 6V above V
CC
,
depending on V
CC
itself. The reason for the maximum
output voltage limit is to avoid switch gate source break-
down due to excessive gate overdrive. A feedback network
is used to limit the charge pump output to 6V above V
CC
.
Because the output will only need to drive the gate of the
external switch by charging and discharging the parasitic
gate capacitances, the internal charge pump, clocked by
an approximately 300KHz oscillator, is appropriately sized
to source less than 100
μ
A.
Power-On Reset and Undervoltage Lockout
The LTC1623 starts up with both gate drives low. An
internal power-on reset (POR) signal inhibits operation
until about 300
μ
s after V
CC
crosses the undervoltage
lockout threshold (typically 2V). The circuit includes some
hysteresis and delay to avoid nuisance resets. Once opera-
tion begins, V
CC
must drop below the threshold for at least
100
μ
s to trigger another POR sequence.
During standby, when both gate drive outputs are dis-
abled, quiescent current is kept to a minimum (13
μ
A
typical) because only the UVLO block is active.
Input Threshold
Anticipating the trend toward lower supply voltages, the
SMBus is specified with a V
IH
of 1.4V and a V
IL
of 0.6V.
While some SMBus parts may violate this stringent SMBus
specification by allowing a higher V
IH
value for a corre-
spondingly higher input supply voltage, the LTC1623
meets and maintains the constant SMBus input threshold
specification across the entire supply voltage range of
2.7V to 5.5V.
Figure 2. LTC1623 Programmed with Address 1011001
1
2
3
4
8
7
6
5
V
CC
GA
GB
AD1
DATA
CLK
AD0
GND
DATA
CLOCK
LTC1623
LOAD1
1M
1M
LOAD2
1623 F02
Table 1. Address Pin Truth Table
AD0
AD1
GND
GND
GND
V
CC
/2
GND
V
CC
V
CC
/2
GND
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
V
CC
GND
V
CC
V
CC
/2
V
CC
V
CC
ADDRESS
1011000
1011001
1011010
1011011
UNUSED
1011100
1011101
1011110
1011111
OPERATIOU
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