參數(shù)資料
型號(hào)： LTC1628I-PG
廠商： Linear Technology Corporation
元件分類： 基準(zhǔn)電壓源/電流源
英文描述： RADIATION HARDENED HIGH EFFICIENCY, 5 AMP SWITCHING REGULATORS
中文描述： 抗輻射高效，5安培開(kāi)關(guān)穩(wěn)壓器
文件頁(yè)數(shù)： 8/32頁(yè)
文件大?。?/td> 375K
代理商： LTC1628I-PG
8
LTC1628-SYNC
RUN/SS1, RUN/SS2 (Pins 1, 15):
Combination of soft-
start, run control inputs and short-circuit detection timers.
A capacitor to ground at each of these pins sets the ramp
time to full output current. Forcing either of these pins
back below 1.0V causes the IC to shut down the circuitry
required for that particular controller. Latchoff overcurrent
protection is also invoked via this pin as described in the
Applications Information section.
SENSE1
+
, SENSE2
+
(Pins 2, 14):
The (+) Input to the
Differential Current Comparators. The I
th
pin voltage and
controlled offsets between the SENSE
–
and SENSE
+
pins
in conjunction with R
SENSE
set the current trip threshold.
SENSE1
–
, SENSE2
–
(Pins 3, 13):
The (–) Input to the
Differential Current Comparators.
V
OSENSE1
, V
OSENSE2
(Pins 4, 12):
Receives the remotely-
sensed feedback voltage for each controller from an
external resistive divider across the output.
PLLFLTR (Pin 5):
The Phase-Locked Loop’s Lowpass
Filter is Tied to This Pin. Alternatively, this pin can be
driven with an AC or DC voltage source to vary the
frequency of the internal oscillator.
PLLIN (Pin 6):
External Synchronization Input to Phase
Detector. This pin is internally terminated to SGND with
50k
. The phase-locked loop will force the rising top gate
signal of controller 1 to be synchronized with the rising
edge of the PLLIN signal.
FCB (Pin 7):
Forced Continuous Control Input. This input
acts on both controllers and is normally used to regulate
a secondary winding. Pulling this pin below 0.8V will
force continuous synchronous operation. Do not leave
this pin floating.
I
TH1,
I
TH2
(Pins 8, 11):
Error Amplifier Output and Switch-
ing Regulator Compensation Point. Each associated chan-
nels’ current comparator trip point increases with this
control voltage.
SGND (Pin 9):
Small Signal Ground common to both
controllers, must be routed separately from high current
grounds to the common (–) terminals of the C
OUT
capacitors.
3.3V
OUT
(Pin 10):
Output of a linear regulator capable of
supplying 10mA DC with peak currents as high as 50mA.
PGND (Pin 20):
Driver Power Ground. Connects to the
sources of bottom (synchronous) N-channel MOSFETs, an-
odes of the Schottky rectifiers and the (–) terminal(s) of C
IN
.
INTV
CC
(Pin 21):
Output of the Internal 5V Linear Low
Dropout Regulator and the EXTV
CC
Switch. The driver and
control circuits are powered from this voltage source. Must
be decoupled to power ground with a minimum of 4.7
μ
F
tantalum or other low ESR capacitor.
EXTV
CC
(Pin 22):
External Power Input to an Internal
Switch Connected to INTV
CC
. This switch closes and
supplies V
CC
power, bypassing the internal
low dropout
regulator, whenever EXTV
CC
is higher than 4.7V. See
EXTV
CC
connection in Applications section. Do not exceed
7V on this pin.
BG1, BG2 (Pins 23, 19):
High Current Gate Drives for
Bottom (Synchronous) N-Channel MOSFETs. Voltage
swing at these pins is from ground to INTV
CC
.
V
IN
(Pin 24):
Main Supply Pin. A bypass capacitor should
be tied between this pin and the signal ground pin.
BOOST1, BOOST2 (Pins 25, 18):
Bootstrapped Supplies
to the Top Side Floating Drivers. Capacitors are connected
between the boost and switch pins and Schottky diodes
are tied between the boost and INTV
CC
pins. Voltage swing
at the boost pins is from INTV
CC
to (V
IN
+ INTV
CC
).
SW1, SW2 (Pins 26, 17):
Switch Node Connections to
Inductors. Voltage swing at these pins is from a Schottky
diode (external) voltage drop below ground to V
IN
.
TG1, TG2 (Pins 27, 16):
High Current Gate Drives for Top
N-Channel MOSFETs. These are the outputs of floating
drivers with a voltage swing equal to INTV
CC
– 0.5V
superimposed on the switch node voltage SW.
PGOOD (Pin 28):
Open-Drain Logic Output. PGOOD is
pulled to ground when the voltage on either V
OSENSE
pin is
not within
±
7.5% of its set point.
PIU
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