參數(shù)資料
型號(hào)： LTC1629C-PG
廠商： Linear Technology Corporation
英文描述： Dual LinCMOS(TM) Timer 14-SOIC
中文描述： 多相，高效率同步降壓型開關(guān)穩(wěn)壓器
文件頁數(shù)： 23/28頁
文件大?。?/td> 330K
代理商： LTC1629C-PG
23
LTC1629/LTC1629-PG
The worst-case power disipated by the synchronous
MOSFET under short-circuit conditions at elevated ambi-
ent temperature and estimated 50
°
C junction temperature
rise is:
P
V
5 5
.
V
V
A
mW
SYNC
=
(
) (
)
(
)
=
5 5
.
1 8
.
5 28
.
1 48 0 013
.
360
2
.
which is much less than normal, full-load conditions.
Incidentally, since the load no longer dissipates power in
the shorted condition, total system power dissipation is
decreased by over 99%.
The duty cycles when the peak RMS input current occurs
is at D = 0.25 and D = 0.75 according to Figure 4. Calculate
the worst-case required RMS input current rating at the
input voltage, which is 5.5V, that provides a duty cycle
nearest to the peak.
From Figure 4, C
IN
will require an RMS current rating of:
=
(
=
4 6
.
C requiredI
A
A
RMS
RMS
)(
)
20
0 23
.
The output capacitor ripple current is calculated by using
the inductor ripple already calculated for each inductor
and multiplying by the factor obtained from Figure3 along
with the calculated duty factor. The output ripple in con-
tinuous mode will be highest at the maximum input
voltage. From Figure 3, the maximum output current ripple
is:
I
V
fL
I
kHz
H
A
COUT
OUT
COUTMAX
=
(
)
=
)
(
)
μ
2
(
)
=
0 34
.
1.
300
1
.
Note that the PolyPhase technique will have its maximum
benefit for input and output ripple currents when the
number of phases times the output voltage is approxi-
mately equal to or greater than the input voltage.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1629. These items are also illustrated graphically in
the layout diagram of Figure11. Check the following in
your layout:
1) Are the signal and power grounds segregated The
LTC1629 signal ground pin should return to the (–) plate
of C
OUT
separately. The power ground returns to the
sources of the bottom N-channel MOSFETs, anodes of the
Schottky diodes, and (–) plates of C
IN
, which should have
as short lead lengths as possible.
2) Does the LTC1629 V
OS+
pin connect to the (+) plate(s)
of C
OUT
Does the LTC1629 V
OS–
pin connect to the (–)
plate(s) of C
OUT
The resistive divider R1, R2 must be
connected between the V
DIFFOUT
and signal ground and
any feedforward capacitor across R1 should be as close as
possible to the LTC1629.
3) Are the SENSE
–
and SENSE
+
leads routed together with
minimum PC trace spacing The filter capacitors between
SENSE
+
and SENSE
–
pin pairs should be as close as
possible to the LTC1629. Ensure accurate current sensing
with Kelvin connections to the sense resistors.
4) Do the (+) plates of C
IN
connect to the drains of the
topside MOSFETs as closely as possible This capacitor
provides the AC current to the MOSFETs. Keep the input
current path formed by the input capacitor, top and bottom
MOSFETs, and the Schottky diode on the same side of the
PC board in a tight loop to minimize conducted and
radiated EMI.
5) Is the INTV
CC
1
μ
F ceramic decoupling capacitor con-
nected closely between
INTV
CC
and the power ground pin
This capacitor carries the MOSFET driver peak currents. A
small value is used to allow placement immediately adja-
cent to the IC.
6) Keep the switching nodes, SW1 (SW2), away from
sensitive small-signal nodes. Ideally the switch nodes
should be placed at the furthest point from the LTC1629.
7) Use a low impedance source such as a logic gate to drive
the PLLIN pin and keep the lead as short as possible.
APPLICATIU
W
U
U
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