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參數(shù)資料
| 型號(hào)： | LTC1642I |
| 廠商： | Linear Technology Corporation |
| 英文描述： | 8-Bit, 40 MSPS ADC Single Ch., Internal S&H, Low Power 24-TSSOP 0 to 70 |
| 中文描述： | 熱插拔控制器 |
| 文件頁(yè)數(shù)： | 5/12頁(yè) |
| 文件大小： | 147K |
| 代理商： | LTC1642I |
5
LTC 1642
APPLICATIO S U
U
Hot Circuit Insertion
W
U
When a circuit board is inserted into a live backplane its
supply bypass capacitors can draw large currents from the
backplane power bus as they charge. These currents can
permanently damage connector pins and can glitch the
backplane supply, resetting other boards in the system.
The LTC1642 limits the charging currents drawn by a
board’s capacitors, allowing safe insertion in a live
backplane.
Power Supply Ramping
In the circuit shown in Figure 1 the LTC1642 and the
external N-channel pass transistor Q1 work together to
limit charging currents. When power is first applied to V
CC
the chip holds Q1’s gate at ground. After a programmable
delay a 25
μ
A current source begins to charge the external
capacitor C2, generating a voltage ramp of 25
μ
A/C2 V/s at
the GATE pin. Because Q1 acts as a source follower while
its gate ramps, the current charging the board’s bypass
capacitance C
LOAD
is limited to 25
μ
AC
LOAD
/C2.
An internal charge pump supplies the 25
μ
A gate current,
ensuring sufficient gate drive to Q1. At 3V V
CC
the mini-
mum gate drive is 4.5V; at 5V V
CC
the minimum is 10V; at
15V V
CC
the minimum is again 4.5V, due to a Zener clamp
from the GATE pin to ground. Resistor R3 limits this
Zener’s transient current during board insertion and re-
moval and protects against high frequency FET oscilla-
tions.
R2
0.010
V
IN
12V
2.5A
The delay before the GATE pin voltage begins ramping is
determined by the system timer. It comprises an external
capacitor C1 from the RST TMR pin to ground; an internal
2
μ
A current source feeding RST TMR from V
CC
; an internal
comparator, with the positive input tied to RST TMR and
the negative input tied to the 1.23V reference; and an
NMOS pull-down. In standby, the NMOS holds RST TMR
at ground; when the timer starts the NMOS turns off and
the RST TMR voltage ramps up as the current source
charges the capacitor. When RST TMR reaches 1.23V the
timer comparator trips; the GATE voltage begins ramping
and RST TMR returns to ground. The ramp time
t needed
to trip the comparator is :
t(ms) = 615C1(
μ
F).
GATE
ON
14
SENSE
15
RESET
5
4
BRK TMR
2
V
CC
16
Q1
FDR9410A
GND
LTC1642
8
RST TMR
3
1642 F01
R3
100
R4
330
C2
0.047
μ
F
C
LOAD
+
C7
0.1
μ
F
C1
0.33
μ
F
C4
0.33
μ
F
ALL RESISTORS
±
5% UNLESS NOTED
RESET DELAY = 200ms
SHORT-CIRCUIT DURATION = 20ms
Figure 1. Supply Control Circuitry
V
OUT
R1
10k
Figure 2. Supply Control Timing
1642 F02
TIME
GATE
SLOPE = 25
μ
A/C(V/s)
RST TMR
V
IN
V
OUT
V
Powering-Up In Current Limit
Ramping the GATE pin voltage indirectlylimits the charg-
ing current to I = 25
μ
AC
LOAD
/C2, where C2 is the external
capacitor connected to the GATE and C
LOAD
is the load
capacitance. If the value of C
LOAD
is uncertain, then a
worst-case design can often result in needlessly long
ramp times, and it may be better to limit the charging
current directly.
Current Limiting and Solid-State Circuit Breaker
The board current can be limited by connecting a sense
resistor between the LTC1642’s V
CC
and SENSE pins. An
internal servo loop adjusts the GATE pin voltage such that
Q1 acts as a constant current source if the voltage drop
across the sense resistor reaches a limit. The voltage limit
across the sense resistor increases as the output charges
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