參數(shù)資料
型號: LTC1658CS8
廠商: LINEAR TECHNOLOGY CORP
元件分類: DAC
英文描述: Low-Power Dual LinCMOS<TM> Timer 20-LCCC -55 to 125
中文描述: SERIAL INPUT LOADING, 12 us SETTLING TIME, 14-BIT DAC, PDSO8
封裝: 0.150 INCH, PLASTIC, SO-8
文件頁數(shù): 6/12頁
文件大?。?/td> 261K
代理商: LTC1658CS8
6
LTC1658
TW U
W
B12
B13
MSB
t
1
t
6
t
9
BX
DUMMY
BX
DUMMY
B0
LSB
B11
t
7
t
2
t
4
t
3
t
8
CLK
D
IN
D
OUT
CS/LD
t
5
1658 TD
B13
PREVIOUS WORD
B13
CURRENT WORD
B11
B12
BX
BX
DEFU
Differential Nonlinearity (DNL):
The difference between
the measured change and the ideal 1LSB change for any
two adjacent codes. The DNL error between any two codes
is calculated as follows:
DNL = (
V
OUT
– LSB)/LSB
Where
V
OUT
is the measured voltage difference between
two adjacent codes.
Digital Feedthrough:
The glitch that appears at the analog
output caused by AC coupling from the digital inputs when
they change state. The area of the glitch is specified in
(nV)(sec).
Gain Error:
Gain error is the difference between the output
of a DAC from its ideal full-scale value after offset error has
been adjusted.
Integral Nonlinearity (INL):
The deviation from a straight
line passing through the endpoints of the DAC transfer
curve (Endpoint INL). Because the output cannot go below
zero, the linearity is measured between full scale and the
lowest code which guarantees the output will be greater
U
than zero. The INL error at a given input code is
calculated
as follows:
INL = [V
OUT
– V
OS
– (V
FS
– V
OS
)(code/16383)]/LSB
Where V
OUT
is the output voltage of the DAC measured at
the given input code.
Least Significant Bit (LSB):
The ideal voltage difference
between two successive codes.
LSB = V
REF
/16384
Resolution (n):
Defines the number of DAC output states
(2
n
) that divide the full-scale range. Resolution does not
imply linearity.
Voltage Offset Error (V
OS
):
Nominally, the voltage at the
output when the DAC is loaded with all zeros. A single
supply DAC can have a true negative offset, but the output
cannot go below zero (see Applications Information).
For this reason, single supply DAC offset is measured at
the lowest code that guarantees the output will be greater
than zero.
相關(guān)PDF資料
PDF描述
LTC1658IMS8 14-Bit Rail-to-Rail Micropower DAC in MSOP
LTC1658IN8 14-Bit Rail-to-Rail Micropower DAC in MSOP
LTC1659CS8 Low-Power Dual LinCMOS<TM> Timer 14-CDIP -55 to 125
LTC1659CMS8 12-Bit Rail-to-Rail Micropower DAC in MSOP Package
LTC1659IS8 12-Bit Rail-to-Rail Micropower DAC in MSOP Package
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