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參數(shù)資料
| 型號(hào)： | LTC1659IS8 |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | DAC |
| 英文描述： | 12-Bit Rail-to-Rail Micropower DAC in MSOP Package |
| 中文描述： | SERIAL INPUT LOADING, 14 us SETTLING TIME, 12-BIT DAC, PDSO8 |
| 封裝： | 0.150 INCH, PLASTIC, SOP-8 |
| 文件頁(yè)數(shù)： | 8/12頁(yè) |
| 文件大小： | 132K |
| 代理商： | LTC1659IS8 |
8
LTC1659
OPERATIOU
Voltage Output
The LTC1659’s rail-to-rail buffered output can source or
sink 5mA over the entire operating temperature range
while pulling to within 300mV of the positive supply
voltage or ground. The output swings to within a few
millivolts of either supply rail when unloaded and has an
equivalent output resistance of 40
when driving a load to
the rails. The output can drive 1000pF without going into
oscillation.
The output swings from 0V to the voltage at the REF pin,
i.e., there is a gain of 1 from the REF to V
OUT
. Please note
if REF is tied to V
CC
the output can only swing to (V
CC
–
V
OS
). See Applications Information.
Serial Interface
The data on the D
IN
input is loaded into the shift register
on the rising edge of the clock. The MSB is loaded first. The
DAC register loads the data from the shift register when
CS/LD is pulled high. The CLK is disabled internally when
CS/LD is high. Note: CLK must be low before CS/LD is
pulled low to avoid an extra internal clock pulse.
The buffered output of the 12-bit shift register is available
on the D
OUT
pin which swings from GND to V
CC
.Multiple
LTC1659s may be daisy-chained together by connecting
the D
OUT
pin to the D
IN
pin of the next chip, while the CLK
and CS/LD signals remain common to all chips in the daisy
chain. The serial data is clocked to all of the chips, then the
CS/LD signal is pulled high to update all of them
simultaneously.
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