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參數(shù)資料
| 型號： | LTC1660CGN#TR |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 18/18頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 10BIT OCTAL MCRPWR 16SSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 設(shè)置時(shí)間： | 30µs |
| 位數(shù)： | 10 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 8 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 1mW |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SSOP |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 8 電壓，單極；8 電壓，雙極 |
| 采樣率（每秒）： | * |
LTC1665/LTC1660
9
166560fa
TIMING DIAGRAM
DIN
DOUT
CS/LD
SCK
A3
A2
X1
A1
X0
166560 F01
A1
X1
X0
t2
t8
t9
t11
t5
t7
t6
t1
t3
t4
Figure 1
OPERATION
Transfer Function
The transfer function is:
VOUT(IDEAL) =
k
256
VREF for the LTC1665
VOUT(IDEAL) =
k
1024
VREF for the LTC1660
where k is the decimal equivalent of the binary DAC input
code and VREF is the voltage at REF (Pin 6).
Power-On Reset
The LTC1665 clears the outputs to zero scale when power
is first applied, making system initialization consistent
and repeatable.
Power Supply Sequencing
The voltage at REF (Pin 6) should be kept within the range
– 0.2V ≤ VREF ≤ VCC + 0.2V (see Absolute Maximum Rat-
ings). Particular care should be taken to observe these
limits during power supply turn-on and turn-off sequences,
when the voltage at VCC (Pin 16) is in transition.
Serial Interface
Referring to Figure 2a (2b): With CS/LD held low, data
on the DIN input is shifted into the 16-bit shift register on
the positive edge of SCK. The 4-bit DAC address, A3-A0,
is loaded first (see Table 2), then the 8-bit (10-bit) input
code, D7-D0 (D9-D0), ordered MSB-to-LSB in each case.
Four (two) don’t-care bits, X3-X0 (X1-X0), are loaded last.
When the full 16-bit input word has been shifted in, CS/LD
is pulled high, loading the DAC register with the word
and causing the addressed DAC output(s) to update. The
clock is disabled internally when CS/LD is high. Note: SCK
must be low before CS/LD is pulled low.
The buffered serial output of the shift register is available
on the DOUT pin, which swings from GND to VCC. Data
appears on DOUT 16 positive SCK edges after being ap-
plied to DIN.
Multiple LTC1665/LTC1660’s can be controlled from a
single 3-wire serial port (i.e., SCK, DIN and CS/LD) by
using the included “daisy-chain” facility. A series of m
chips is configured by connecting each DOUT (except the
last) to DIN of the next chip, forming a single 16m-bit
shift register. The SCK and CS/LD signals are common
to all chips in the chain. In use, CS/LD is held low while m
16-bit words are clocked to DIN of the first chip; CS/LD
is then pulled high, updating all of them simultaneously.
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