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參數(shù)資料
| 型號： | LTC1662IMS8#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 10BIT ULP BUFFERED 8-MSOP |
| 標準包裝： | 50 |
| 設(shè)置時間： | 400µs |
| 位數(shù)： | 10 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 260µW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-MSOP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 2 電壓，單極 |
| 采樣率（每秒）： | * |
| 產(chǎn)品目錄頁面： | 1350 (CN2011-ZH PDF) |
LTC1662
4
1662fa
timing characteristics The
l
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VCC = 4.5V to 5.5V
t1
SDI Setup
Relative to SCK Positive Edge
l
55
ns
t2
SDI Hold
Relative to SCK Positive Edge
l
0
ns
t3
SCK High Time
(Note 6)
l
30
ns
t4
SCK Low Time
(Note 6)
l
30
ns
t5
CS/LD Pulse Width
(Note 6)
l
100
ns
t6
LSB SCK High to CS/LD High
(Note 6)
l
30
ns
t7
CS/LD Low to SCK High
(Note 6)
l
20
ns
t9
SCK Low to CS/LD Low
(Note 6)
l
0
ns
t11
CS/LD High to SCK Positive Edge
(Note 6)
l
20
ns
SCK Frequency
Square Wave (Note 6)
l
16.7
MHz
VCC = 2.7V to 5.5V
t1
SDI Setup
Relative to SCK Positive Edge (Note 6)
l
75
ns
t2
SDI Hold
Relative to SCK Positive Edge (Note 6)
l
0
ns
t3
SCK High Time
(Note 6)
l
50
ns
t4
SCK Low Time
(Note 6)
l
50
ns
t5
CS/LD Pulse Width
(Note 6)
l
150
ns
t6
LSB SCK High to CS/LD High
(Note 6)
l
50
ns
t7
CS/LD Low to SCK High
(Note 6)
l
30
ns
t9
SCK Low to CS/LD Low
(Note 6)
l
0
ns
t11
CS/LD High to SCK Positive Edge
(Note 6)
l
30
ns
SCK Frequency
Square Wave (Note 6)
l
10
MHz
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Nonlinearity and monotonicity are defined and tested at VCC = 5V,
VREF = 4.096V, from code 20 to code 1023. See Figure 2.
Note 3: Digital inputs at 0V or VCC.
Note 4: Load is 10kΩ in parallel with 100pF.
Note 5: VCC = VREF = 5V. DAC switched between 0.1VFS and 0.9VFS;
i.e., codes k = 102 and k = 922.
Note 6: Guaranteed by design, not subject to test.
Note 7: One DAC output loaded.
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