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參數(shù)資料
| 型號： | LTC1663 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | 10-Bit, 12.5 us DAC, Serial Input, Low Power 8-MSOP 0 to 70 |
| 中文描述： | 10位軌至軌微DAC，帶有2線接口 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 195K |
| 代理商： | LTC1663 |
5
LTC1663
V
CC
(Pin 5, Pin 4 on SOT-23):
Power Supply. 2.7V
≤
V
CC
≤
5.5V. Also used as the reference voltage input when the
part is programmed to use V
CC
as the reference.
AD0 (Pin 6):
Slave Address Select Bit 0. Tie this pin to
either V
CC
or GND to modify the corresponding bit of the
LTC1663’s slave address.
GND (Pin 7, Pin 2 on SOT-23):
System Ground.
V
OUT
(Pin 8, Pin 3 on SOT-23):
Voltage Output. Buffered
rail-to-rail DAC output.
PI
FU
CTIO
N
S
U
U
SDA (Pin 1, Pin 1 on SOT-23):
Serial Data Bidirectional
Pin. Data is shifted into the SDA pin and acknowledged by
the SDA pin. High impedance pin while data is shifted in.
Open-drain N-channel output during acknowledgment.
Requires a pull-up resistor or current source to V
CC
.
AD1 (Pin 2):
Slave Address Select Bit 1. Tie this pin to
either V
CC
or GND to modify the corresponding bit of the
LTC1663’s slave address.
AD2 (Pin 3):
Slave Address Select Bit 2. Tie this pin to
either V
CC
or GND to modify the corresponding bit of the
LTC1663’s slave address.
SCL (Pin 4, Pin 5 on SOT-23):
Serial Clock Input Pin. Data
is shifted into the SDA pin at the rising edges of the clock.
This high impedance pin requires a pull-up resistor or
current source to V
CC
.
DEFI
ITIO
N
S
U
Differential Nonlinearity (DNL):
The difference between
the measured change and the ideal 1LSB change for any
two adjacent codes. The DNL error between any two codes
is calculated as follows:
DNL = (
V
OUT
– LSB)/LSB
Where
V
OUT
is the measured voltage difference between
two adjacent codes.
Digital Feedthrough:
The glitch that appears at the analog
output caused by AC coupling from the digital inputs when
they change state. The area of the glitch is specified in
(nV)(sec).
Full-Scale Error (FSE):
The deviation of the actual full-
scale voltage from ideal. FSE includes the effects of offset
and gain errors (see Applications Information).
Integral Nonlinearity (INL):
The deviation from a straight
line passing through the endpoints of the DAC transfer
curve (Endpoint INL). Because the output cannot go below
zero, the linearity is measured between full scale and the
lowest code that guarantees the output will be greater than
zero. The INL error at a given input code is
calculated as
follows:
INL = [V
OUT
– V
OS
– (V
FS
– V
OS
)(code/1023)]/LSB
Where V
OUT
is the output voltage of the DAC measured at
the given input code.
Least Significant Bit (LSB):
The ideal voltage difference
between two successive codes.
LSB = V
REF
/1024
Resolution (n):
Defines the number of DAC output states
(2
n
) that divide the full-scale range. Resolution does not
imply linearity.
Voltage Offset Error (V
OS
):
Nominally, the voltage at the
output when the DAC is loaded with all zeros. A single
supply DAC can have a true negative offset, but the output
cannot go below zero (see Applications Information).
For this reason, single supply DAC offset is measured at
the lowest code that guarantees the output will be greater
than zero.
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|---|---|
| LTC1663-1CS5 | 制造商:Linear Technology 功能描述:DAC 1-CH 10-bit 5-Pin TSOT-23 |
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| LTC1663-1CS5#TRM | 功能描述:IC DAC 10BIT R-R TSOT23-5 RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1,000 系列:- 設(shè)置時(shí)間:1µs 位數(shù):8 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:8 電壓電源:雙 ± 功率耗散（最大）:941mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC W 包裝:帶卷 (TR) 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:* |
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