參數(shù)資料
型號(hào): LTC1663CMS8
廠商: LINEAR TECHNOLOGY CORP
元件分類: DAC
英文描述: 10-Bit, 12.5 us DAC, Serial Input, Low Power 8-SOIC 0 to 70
中文描述: SERIAL INPUT LOADING, 30 us SETTLING TIME, 10-BIT DAC, PDSO8
封裝: PLASTIC, MSOP-8
文件頁(yè)數(shù): 3/12頁(yè)
文件大?。?/td> 195K
代理商: LTC1663CMS8
3
LTC1663
ELECTRICAL C
temperature range, otherwise specifications are at T
A
= 25
°
C. V
CC
= 2.7V to 5.5V, V
CC
set as reference, V
OUT
unloaded,
unless otherwise noted.
HARA TERISTICS
The
G
denotes specifications which apply over the full operating
The
G
denotes specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25
°
C. V
CC
= 2.7V to 5.5V, V
CC
set as reference, V
OUT
unloaded, unless otherwise noted.
TI I G CHARACTERISTICS
U
W
Note 1:
Absolute maximum ratings are those values beyond which the life
of a device may be impaired.
Note 2:
Nonlinearity and monotonicity are defined from code 20 to code
1003 (full scale). See Applications Information.
Note 3:
Digital inputs at 0V or V
CC
.
Note 4:
Load is 10k
in parallel with 100pF.
Note 5:
V
CC
= V
REF
= 5V. DAC switched between 0.1V
FS
and 0.9V
FS
,
i.e., codes k = 102 and k = 922.
Note 6:
All values are referenced to V
IH
and V
IL
levels.
Note 7:
Guaranteed by design and not subject to test.
SYMBOL
SMBus Timing Characteristics (Notes 6, 7)
f
SMB
SMBus Operating Frequency
t
BUF
Bus Free Time Between Stop and Start Condition
t
HD, STA
Hold Time After (Repeated) Start Condition
t
SU, STA
Repeated Start Condition Setup Time
t
SU, STO
Stop Condition Setup Time
t
HD, DAT
Data Hold Time
t
SU, DAT
Data Setup Time
t
LOW
Clock Low Period
t
HIGH
Clock High Period
t
f
Clock, Data Fall Time
t
r
Clock, Data Rise Time
PARAMETER
MIN
TYP
MAX
UNITS
G
10
4.7
4.0
4.7
4.0
300
250
4.7
4.0
100
kHz
μ
s
μ
s
μ
s
μ
s
ns
ns
μ
s
μ
s
ns
ns
G
G
G
G
G
G
G
G
50
300
1000
G
G
SYMBOL
PARAMETER
Output Impedance to V
CC
CONDITIONS
Input Code = 1023, V
CC
= 5V
Input Code = 1023, V
CC
= 3V
MIN
TYP
80
120
MAX
UNITS
AC Performance
Voltage Output Slew Rate
Rising (Notes 4, 5)
Falling (Notes 4, 5)
To
±
0.5LSB (Notes 4, 5)
0.75
0.25
30
0.75
70
V/
μ
s
V/
μ
s
μ
s
nV s
nV s
Voltage Output Settling Time
Digital Feedthrough
Digital-to-Analog Glitch Impulse
Digital Inputs SCL, SDA
V
IH
High Level Input Voltage
V
IL
Low Level Input Voltage
V
LTH
Logic Threshold Voltage
I
LEAK
Digital Input Leakage
C
IN
Digital Input Capacitance
Digital Output SDA
V
OL
Digital Output Low Voltage
Address Inputs AD0, AD1, AD2 (MSOP Only)
I
UP
Address Pin Pull-Up Current
V
IH
High Level Input Voltage
V
IL
Low Level Input Voltage
1LSB Change Around Major Carry
G
1.4
V
V
V
G
0.6
1
V
CC
= 5.5V and 0V, V
IN
= GND to V
CC
(Note 7)
G
±
1
10
μ
A
pF
G
I
PULLUP
= 350
μ
A
G
0.4
V
V
IN
= 0V
G
G
V
CC
– 0.3
G
0.5
1.5
μ
A
V
V
0.8
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