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參數(shù)資料
| 型號： | LTC1663IMS8#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 12/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC D/A CONV 10BIT R-R 8-MSOP |
| 標準包裝： | 2,500 |
| 設置時間： | 30µs |
| 位數(shù)： | 10 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 630µW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應商設備封裝： | 8-MSOP |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 1 電壓，單極 |
| 采樣率（每秒）： | * |
LTC1663
9
1663fd
APPLICATIONS INFORMATION
Data Bytes
Least Signicant Data Byte
76
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Most Signicant Data Byte
7
6
54
32
1
0
X
XX
D9
D8
X = Don’t care
Send Byte Protocol
The Send Byte protocol used on the LTC1663 is actually a
subset of the Write Word protocol described previously.
The Send Byte protocol can only be used to send the
command byte information to the LTC1663.
Command Byte
A
Slave Address
A
Wr
P
S
81
1
71
1
1663 TA04
1
S = Start Condition, Wr = Write Bit, A = Acknowledge, P = Stop Condition
The Send Byte protocol is also used whenever the Write
Word protocol is interrupted for any reason. Reception of
a START or STOP condition after the Acknowledge of the
command byte, but before the Acknowledge of the last
data byte, will cause both data bytes to be ignored and
the command byte to be accepted.
Reception of a START or STOP condition before the Ac-
knowledge of the command byte will cause the interrupted
command byte to be ignored.
SYNC Address/Quick Command
In addition to the slave address, the LTC1663 has an address
that can be shared by other devices so that they may be
updated synchronously. The address is called to the SYNC
address and uses the quick command protocol.
The SYNC Address is 1111 110
Ack
Stop
Start
1111 110
SY/CLR
11
71
1663 TA05
1
SYNC Address
SY/CLR
1
0
Update output latches on rising edge of SCL during
Acknowledge of SYNC Address
Clear all internal latches on rising edge of SCL during
Acknowledge of SYNC Address
The SY/CLR bit set high only has meaning when the “SY”
bit of the command byte was previously set HIGH. On
the otherhand, the SY/CLR bit set LOW will always clear
the part, independent of the state of the “SY” bit in the
command byte.
Input Threshold
Anticipating the trend toward lower supply voltages,
the SMBus is specied with a VIH of 1.4V and a VIL of
0.6V. While some SMBus parts may violate this stringent
SMBus specication by allowing a higher VIH value for a
correspondingly higher input supply voltage, the LTC1663
meets and maintains the constant SMBus input threshold
specication across the entire supply voltage range of
2.7V to 5.5V. The logic input threshold is designed to be
1V with 50mV of hysteresis.
Voltage Output
The output amplier contained in the LTC1663 can source
or sink up to 5mA. The output stage swings to within a
few millivolts of either supply rail when unloaded and
has an equivalent output resistance of 85Ω when driving
a load to the rails. The output amplier is stable driving
capacitive loads up to 1000pF.
A small resistor placed in series with the output can be
used to achieve stability for any load capacitance greater
than 1000pF. For example, a 0.1μF load can be driven
by the LTC1663 if a 110Ω series resistance is used. The
phase margin of the resulting circuit is 45° and increases
monotonically from this point if larger values of resistance,
capacitance or both are substituted for the values given.
Rail-to-Rail Output Considerations
As in any rail-to-rail device, the output is limited to volt-
ages within the supply range.
If the DAC offset is negative, the output for the lowest
codes limits at 0V as shown in Figure 1b.
Similarly, limiting can occur near full scale when VCC is
used as the reference. If VREF = VCC and the DAC full-scale
error (FSE) is positive, the output for the highest codes
limits at VCC as shown in Figure 1c. No full-scale limiting
can occur if the internal reference is used.
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