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參數(shù)資料
| 型號(hào)： | LTC1664IGN |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | DAC |
| 英文描述： | Micropower Quad 10-Bit DAC |
| 中文描述： | QUAD, SERIAL INPUT LOADING, 19 us SETTLING TIME, 10-BIT DAC, PDSO16 |
| 封裝： | 0.150 INCH, PLASTIC, SSOP-16 |
| 文件頁數(shù)： | 8/16頁 |
| 文件大?。?/td> | 168K |
| 代理商： | LTC1664IGN |
8
LTC 1664
A3 A2 A1
Address/Control
A0 D9 D8 D7 D6 D5 D4 D3 D2 D1
X1 X0
D0
Input Code
Don’t
Care
Table 1. LTC1664 Input Word
OPERATIOU
Transfer Function
The transfer function is
V
k
V
OUT IDEAL
(
REF
)
=
1024
where k is the decimal equivalent of the binary DAC input
code and V
REF
is the voltage at REF (Pin 6).
Power-On Reset
The LTC1664 clears the outputs to zero scale when power
is first applied, making system initialization consistent and
repeatable.
Power Supply Sequencing
The voltage at REF (Pin 6) should be kept within the range
–0.2V
≤
V
REF
≤
V
CC
+ 0.2V (see Absolute Maximum
Ratings). Particular care should be taken to observe these
limits during power supply turn-on and turn-off sequences,
when the voltage at V
CC
(Pin 16) is in transition.
Serial Interface
Referring to Figure 2: With CS/LD held low, data on the D
IN
input is shifted into the 16-bit shift register on the positive
edge of
SCK
. The 4-bit DAC address, A3-A0, is loaded first
(see Table 2), then the 10-bit input code, D9-D0, ordered
MSB-to-LSB in each case. Two don’t-care bits, X1-X0, are
loaded last. When the full 16-bit input word has been
shifted in, CS/LD is pulled high, loading the DAC register
with the word and causing the addressed DAC output(s)
to update. The clock is disabled internally when CS/LD is
high. Note:
SCK
must be low before CS/LD is pulled low.
The buffered serial output of the shift register is available
on the D
OUT
pin, which swings from GND to V
CC
. Data
appears on D
OUT
16 positive SCK edges after being applied
to D
IN
.
Multiple LTC1664’s can be controlled from a single 3-wire
serial port (i.e., SCK, D
IN
and CS/LD) by using the included
“daisy-chain” facility. A series of mchips is configured by
connecting each D
OUT
(except the last) to D
IN
of the next
chip, forming a single 16mbit shift register. The SCK and
CS/LD signals are common to all chips in the chain. In use,
CS/LD is held low while m16-bit words are clocked to D
IN
of the first chip; CS/LD is then pulled high, updating all of
them simultaneously.
Sleep Mode
DAC address 1110
b
is reserved for the special Sleep
instruction (see Table 2). In this mode, the digital interface
stays active while the analog circuits are disabled; static
power consumption is thus virtually eliminated. The refer-
ence input and analog outputs are set in a high impedance
state and all DAC settings are retained in memory so that
when Sleep mode is exited, the outputs of DACs not
updated by the Wake command are restored to their last
active state.
Sleep mode is initiated by performing a load sequence to
address 1110
b
(the DAC input word D9-D0 is ignored).
Once in Sleep mode, a load sequence to any other address
(including “No Change” addresses 0000
b
and 1001-1101
b
)
causes the LTC1664 to Wake. It is possible to keep one or
more chips of a daisy chain in continuous Sleep mode by
giving the Sleep instruction to these chips each time the
active chips in the chain are updated.
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