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參數(shù)資料
| 型號： | LTC1665C |
| 廠商： | Linear Technology Corporation |
| 英文描述： | 10-Bit, 12.5 us DAC, Serial Input, Low Power 8-SOIC -40 to 85 |
| 中文描述： | 微八進制8位和10位DAC |
| 文件頁數(shù)： | 8/16頁 |
| 文件大小： | 209K |
| 代理商： | LTC1665C |
8
LTC1665/LTC1660
TIW
W
Figure 1
OPERATIOU
Transfer Function
The transfer function is
V
k
V
for theLTC
V
k
V
for theLTC
OUT IDEAL
(
REF
OUT IDEAL
(
REF
)
)
=
=
256
1665
1024
1660
where k is the decimal equivalent of the binary DAC input
code and V
REF
is the voltage at REF (Pin 6).
Power-On Reset
The LTC1665 clears the outputs to zero scale when power
is first applied, making system initialization consistent and
repeatable.
Power Supply Sequencing
The voltage at REF (Pin 6) should be kept within the range
–0.2V
≤
V
REF
≤
V
CC
+ 0.2V (see Absolute Maximum
Ratings). Particular care should be taken to observe these
limits during power supply turn-on and turn-off sequences,
when the voltage at V
CC
(Pin 16) is in transition.
Serial Interface
Referring to Figure 2a (2b): With CS/LD held low, data on
the D
IN
input is shifted into the 16-bit shift register on the
positive edge of
SCK
. The 4-bit DAC address, A3-A0, is
loaded first (see Table 2), then the 8-bit (10-bit) input
code, D7-D0 (D9-D0), ordered MSB-to-LSB in each case.
Four (two) don’t-care bits, X3-X0 (X1-X0), are loaded last.
When the full 16-bit input word has been shifted in, CS/LD
is pulled high, loading the DAC register with the word and
causing the addressed DAC output(s) to update. The
clock is disabled internally when CS/LD is high. Note:
SCK
must be low before CS/LD is pulled low.
The buffered serial output of the shift register is available
on the D
OUT
pin, which swings from GND to V
CC
. Data
appears on D
OUT
16 positive SCK edges after being applied
to D
IN
.
Multiple LTC1665/LTC1660’s can be controlled from a
single 3-wire serial port (i.e., SCK, D
IN
and CS/LD) by
using the included “daisy-chain” facility. A series of m
chips is configured by connecting each D
OUT
(except the
last) to D
IN
of the next chip, forming a single 16m-bit shift
register. The SCK and CS/LD signals are common to all
D
IN
D
OUT
CS/LD
SCK
A3
A3
A3
A2
A2
X1
A1
X0
1665/60 F01
A1
X1
X0
t
2
t
8
t
9
t
11
t
5
t
7
t
6
t
1
t
3
t
4
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