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參數(shù)資料
| 型號(hào)： | LTC1665I |
| 廠商： | Linear Technology Corporation |
| 英文描述： | 10-Bit, 12.5 us DAC, Serial Input, Low Power 8-PDIP -40 to 85 |
| 中文描述： | 微八進(jìn)制8位和10位DAC |
| 文件頁數(shù)： | 10/16頁 |
| 文件大小： | 209K |
| 代理商： | LTC1665I |
10
LTC1665/LTC1660
OPERATIOU
Table 2. DAC Address/Control Functions
ADDRESS/CONTROL
A3
A2
A1
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DAC STATUS
No Change
Load DAC A
Load DAC B
Load DAC C
Load DAC D
Load DAC E
Load DAC F
Load DAC G
Load DAC H
No Change
No Change
No Change
No Change
No Change
No Change
Load
ALL
DACs
with Same
8/10-Bit Code
SLEEP STATUS
Wake
Wake
Wake
Wake
Wake
Wake
Wake
Wake
Wake
Wake
Wake
Wake
Wake
Wake
Sleep
Wake
state and all DAC settings are retained in memory so that
when Sleep mode is exited, the outputs of DACs not
updated by the Wake command are restored to their last
active state.
Sleep mode is initiated by performing a load sequence to
address 1110
b
(the DAC input word D7-D0 [D9-D0] is
ignored). Once in Sleep mode, a load sequence to any
other address (including “No Change” addresses 0000
b
and 1001-1101
b
) causes the LTC1665/LTC1660 to Wake.
It is possible to keep one or more chips of a daisy chain in
continuous Sleep mode by giving the Sleep instruction to
these chips each time the active chips in the chain are
updated.
Voltage Outputs
Each of the eight rail-to-rail output amplifiers contained in
these parts can source or sink up to 5mA. The outputs
swing to within a few millivolts of either supply rail when
unloaded and have an equivalent output resistance of 85
when driving a load to the rails. The output amplifiers are
stable driving capacitive loads up to 1000pF.
A small resistor placed in series with the output can be
used to achieve stability for any load capacitance. A 1
μ
F
load can be successfully driven by inserting a 20
resis-
tor; a 2.2
μ
F load needs only a 10
resistor. In either case,
larger values of resistance, capacitance or both may be
safely substituted for the values given.
Rail-to-Rail Output Considerations
In any rail-to-rail output voltage DAC, the output is limited
to voltages within the supply range.
If the DAC offset is negative, the output for the lowest
codes limits at 0V as shown in Figure 3b.
Similarly, limiting can occur near full scale when the REF
pin is tied to V
CC
. If V
REF
= V
CC
and the DAC full-scale error
(FSE) is positive, the output for the highest codes limits at
V
CC
as shown in Figure 3c. No full-scale limiting can occur
if V
REF
is less than V
CC
– FSE.
Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting can
occur.
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