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參數(shù)資料
| 型號(hào)： | LTC1668IG#TR |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 3/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 16BIT 50MSPS 28SSOP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 設(shè)置時(shí)間： | 20ns |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 雙 ± |
| 功率耗散（最大）： | 180mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SSOP |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 2 電流，單極 |
| 采樣率（每秒）： | 50M |
| 配用： | DC245A-A-ND - BOARD EVAL LTC1668 |
11
LTC1666/LTC1667/LTC1668
APPLICATIO S I FOR ATIO
WU
UU
Theory of Operation
The LTC1666/LTC1667/LTC1668 are high speed current
steering 12-/14-/16-bit DACs made on an advanced
BiCMOS process. Precision thin film resistors and well
matched bipolar transistors result in excellent DC linearity
and stability. A low glitch current switching design gives
excellent AC performance at sample rates up to 50Msps.
The devices are complete with a 2.5V internal bandgap
reference and edge triggered latches, and set a new
standard for DAC applications requiring very high dy-
namic range at output frequencies up to several mega-
hertz.
Referring to the Block Diagrams, the DACs contain an
array of current sources that are steered to IOUTA or IOUTB
with NMOS differential current switches. The four most
significant bits are made up of 15 current segments of
equal weight. The remaining lower bits are binary weighted,
using a combination of current scaling and a differential
resistive attenuator ladder. All bits and segments are
precisely matched, both in current weight for DC linearity,
and in switch timing for low glitch impulse and low
spurious tone AC performance.
Setting the Full-Scale Current, IOUTFS
The full-scale DAC output current, IOUTFS, is nominally
10mA, and can be adjusted down to 1mA. Placing a
resistor, RSET, between the REFOUT pin, and the IREFIN pin
sets IOUTFS as follows.
The internal reference control loop amplifier maintains a
virtual ground at IREFIN by servoing the internal current
source, IINT, to sink the exact current flowing into IREFIN.
IINT is a scaled replica of the DAC current sources and
IOUTFS = 8 (IINT), therefore:
IOUTFS = 8 (IREFIN) = 8 (VREF/RSET)
(1)
For example, if RSET = 2k and is tied to VREF = REFOUT =
2.5V, IREFIN = 2.5/2k = 1.25mA and IOUTFS = 8 (1.25mA)
= 10mA.
The reference control loop requires a capacitor on the
COMP1 pin for compensation. For optimal AC perfor-
mance, CCOMP1 should be connected to VSS and be placed
very close to the package (less than 0.1").
For fixed reference voltage applications, CCOMP1 should
be 0.1
F or more. The reference control loop small-signal
bandwidth is approximately 1/(2
π)CCOMP180or20kHz
for CCOMP1 = 0.1F.
Reference Operation
The onboard 2.5V bandgap voltage reference drives the
REFOUT pin. It is trimmed and specified to drive a 2k
resistor tied from REFOUT to IREFIN, corresponding to a
1.25mA load (IOUTFS = 10mA). REFOUT has nominal
output impedance of 6
, or 0.24% per mA, so it must be
buffered to drive any additional external load. A 0.1
F
capacitor is required on the REFOUT pin for compensa-
tion. Note that this capacitor is required for stability, even
if the internal reference is not being used.
External Reference Operation
Figure 1, shows how to use an external reference to control
the LTC1666/LTC1667/LTC1668 full-scale current.
Figure 1. Using the LTC1666/LTC1667/LTC1668
with an External Reference
REFOUT
+
–
IREFIN
2.5V
REFERENCE
RSET
0.1
F
5V
1666/7/8 F02
EXTERNAL
REFERENCE
LTC1666/
LTC1667/
LTC1668
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