APPLICATIONS INFOR
參數(shù)資料
型號(hào): LTC1685CS8#PBF
廠商: Linear Technology
文件頁數(shù): 2/12頁
文件大?。?/td> 0K
描述: IC TXRX RS485 PREC DELAY 8-SOIC
標(biāo)準(zhǔn)包裝: 100
類型: 收發(fā)器
驅(qū)動(dòng)器/接收器數(shù): 1/1
規(guī)程: RS422,RS485
電源電壓: 4.75 V ~ 5.25 V
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SOIC
包裝: 管件
產(chǎn)品目錄頁面: 1354 (CN2011-ZH PDF)
10
LTC1685
APPLICATIONS INFORMATION
WU
U
Very inexpensive unshielded telephone grade twisted pair
is shown in Figure 13. In spite of the noticeable loss at the
receiver input, the LTC1685 can still transfer 30Mbps at
100ft of telephone grade UTP. Note that under all these
conditions, the LTC1685 can pass through a single data
pulse equal to the inverse of the data rate (e.g., 20ns for
50Mbps data rate).
Even at distances of 4000ft, 1Mbps data rates are possible
using the LTC1685 and category 5 UTP. Figure 14a shows
a 1
s pulse propagated down 4000ft of category 5 UTP.
Notice both the DC and the AC losses at the receiver input.
The DC attenuation is due to the parasitic resistance of the
cable. Figure 14b shows a 1Mbps square wave over
4000ft. To transmit at this speed but using longer cable
lengths, see the LTC1686/LTC1687 high speed RS485
full-duplex transceivers.
Figure 13. 100ft of Telephone Grade UTP: 30Mbps
Figure 12. 1000ft of Category 5 UTP: 4Mbps
1685 F13
DRIVER INPUT
DIFFERENTIAL
RECEIVER
INPUT
RECEIVER
OUTPUT
20ns/DIV
2V/DIV
1685 F12
DRIVER
INPUT
RECEIVER
OUTPUT
100ns/DIV
2V/DIV
Figure 14b. 4000ft of Category 5 UTP: 1Mbps Square Wave
Figure 14a. 4000ft of Category 5 UTP: 1
s Pulse
High Speed Backplane Transmission
The LTC1685 can also be used in backplane point-to-point
transceiver applications, where the user wants to assure
operation even when the common mode goes above or
below the rails. It is advisable to terminate the PC traces
when approaching maximum speeds. Since the LTC1685
is not intended to drive parallel terminated cables with
characteristic impedances much less than that of twisted
pair, both ends of the PC trace must be
series terminated
with the characteristic impedance of the trace. For best
results, the signal should be routed differentially. The true
and complement outputs of the LTC1685 should be routed
on adjacent layers of the PC board. The two traces should
be routed very symmetrically, minimizing and equalizing
parasitics to nearby signal and power/ground layers. For
single-ended transmission, route the series terminated
1685 F14a
RECEIVER
INPUT
DRIVER
INPUT
RECEIVER
OUTPUT
1
s/DIV
1V/DIV
5V/DIV
2V/DIV
CABLE DELAY
1685 F14b
DRIVER
INPUT
RECEIVER
OUTPUT
1
s/DIV
5V/DIV
2V/DIV
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