參數(shù)資料
型號: LTC1695CS5
廠商: LINEAR TECHNOLOGY CORP
元件分類: 運動控制電子
英文描述: SMBus/I2C Fan Speed Controller in SOT-23
中文描述: BRUSHLESS DC MOTOR CONTROLLER, PDSO5
封裝: PLASTIC, SC-74A, SOT-23, 5 PIN
文件頁數(shù): 10/20頁
文件大小: 227K
代理商: LTC1695CS5
LTC1695
10
DEFINITIONS
Resolution:
The number of DAC output states (2
N
) that
divide the full-scale range. The resolution does not imply
linearity.
Full-Scale Voltage (V
FS
):
The regulator output voltage
(V
OUT
) if all DAC bits are set to ones (code 63).
Voltage Offset Error (V
OS
):
The regulator output voltage
if all DAC bits are set to zeros. The LDO amplifier can have
a true negative offset, but due to the LTC1695’s single
supply operation, V
OUT
cannot go below ground. If the
offset is negative, V
OUT
will remain near 0V resulting in the
transfer curve shown in Figure 1.
Table 1. Nominal V
LSB
and V
FS
values
V
CC
4.5V
5.0V
5.5V
V
LSB
70.3mV
78.1mV
85.9mV
V
FS
4.430V
4.922V
5.414V
INL:
Integral nonlinearity is the maximum deviation from
a straight line passing through the endpoints of the DAC
transfer curve. Due to the LTC1695’s single supply opera-
tion and the fact that V
OUT
cannot go below ground,
linearity is measured between full scale and the first code
(code 01) that guarantees a positive output. The INL error
at a given input code is calculated as follows:
INL = (V
OUT
– V
IDEAL
))/V
LSB
V
IDEAL
= (Code V
LSB
) + V
OS
V
OUT
= The output voltage of the DAC
measured at the given input code
DNL:
Differential nonlinearity is the difference between the
measured change and the ideal 1LSB change between any
two adjacent codes. The DNL error between any two codes
is calculated as below:
DNL = (
V
OUT
– V
LSB
)/V
LSB
V
OUT
= The measured voltage difference
between two adjacent codes
The
V
OUT
calculation includes the V
OS
values to account
for the effect of negative offset in Figure 1. This is relevant
for code 1’s DNL.
The offset of the part is measured at the first code (code1)
that produces an output voltage 0.5LSB greater than the
previous code.
V
OS
= V
OUT
– [(Code V
FS
)/(2
N
– 1)]
Least Significant Bit (V
LSB
):
The least significant bit or the
ideal voltage difference between two successive codes.
V
LSB
= (V
FS
– V
OS
)/(2
N
– 1)
Figure 1. Effect of Negative Offset
OUTPUT
VOLTAGE
DAC CODE
0V
NEGATIVE
OFFSET
1695 F01
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