參數(shù)資料
型號(hào)： LTC1702
廠商： Linear Technology Corporation
元件分類： 通用總線功能
英文描述： Synchronous 8-Bit Up/Down Binary Counters 24-SOIC 0 to 70
中文描述： 雙550kHz的同步二相開關(guān)穩(wěn)壓器控制器
文件頁(yè)數(shù)： 16/36頁(yè)
文件大?。?/td> 350K
代理商： LTC1702
16
LTC1702
FAULT mode is used, a Schottky diode should be added
with its cathode at the output and its anode at ground to
clamp the negative voltage to a safe level and prevent
possible damage to the load and the output capacitors.
Note that in overvoltage conditions, the MAX comparator
will kick in at just +5%, turning QB on continuously long
before the output reaches +15%. Under most fault condi-
tions, this is adequate to bring the output back down
without firing the fault latch. Additionally, if MAX success-
fully keeps the output below +15%, the LTC1702 will
resume normal regulation as soon as the output overvolt-
age fault is resolved.
In some circuits, the OV latch can be a liability. Consider
a circuit where the output voltage at one channel may be
changed on the fly by switching in different feedback
resistors. A downward adjustment of greater than 15%
will fire the fault latch, disabling both sides of the LTC1702
until the power is recycled. In circuits such as this, the fault
latch can be disabled by grounding the FAULT pin. The
internal latch will still be set the first time the output
exceeds +15%, but the 10
μ
A current source pull-up will
not be able to pull FAULT high, and the LTC1702 will ignore
the latch and continue normal operation. The MAX com-
parator will act as usual, turning on QB until output is
within range and then allowing the loop to resume normal
operation. FAULT can also be pulled down with external
open-collector logic to restart a fault-latched LTC1702 as
an alternative to recycling the power. Note that this will not
reset the internal latch; if the external pull-down is
released, the LTC1702 will reenter FAULT mode. To reset
the latch, pull both RUN/SS pins low simultaneously or
cycle the input power.
EXTERNAL COMPONENT SELECTION
POWER MOSFETs
Getting peak efficiency out of the LTC1702 depends strongly
on the external MOSFETs used. The LTC1702 requires at
least two external MOSFETs per side—more if one or
more of the MOSFETs are paralleled to lower on-resis-
tance. To work efficiently, these MOSFETs must exhibit
low R
DS(ON)
at 5V V
GS
(3.3V V
GS
if the PV
CC
input supply
APPLICATIO
S I
N
FOR
ATIO
U
W
U
is 3.3V) to minimize resistive power loss while they are
conducting current. They must also have low gate charge
to minimize transition losses during switching. On the
other hand, voltage breakdown requirements in a typical
LTC1702 circuit are pretty tame: the 7V maximum input
voltage limits the V
DS
and V
GS
the MOSFETs can see to
safe levels for most devices.
Low R
DS(ON)
R
DS(ON)
calculations are pretty straightforward. R
DS(ON)
is
the resistance from the drain to the source of the MOSFET
when the gate is fully on. Many MOSFETs have R
DS(ON)
specified at 4.5V gate drive—this is the right number to
use in LTC1702 circuits running from a 5V supply. As
current flows through this resistance while the MOSFET is
on, it generates I
2
R watts of heat, where I is the current
flowing (usually equal to the output current) and R is the
MOSFET R
DS(ON)
. This heat is only generated when the
MOSFET is on. When it is off, the current is zero and the
power lost is also zero (and the other MOSFET is busy
losing power).
This lost power does two things: it subtracts from the
power available at the output, costing efficiency, and it
makes the MOSFET hotter—both bad things. The effect is
worst at maximum load when the current in the MOSFETs
and thus the power lost are at a maximum. Lowering
R
DS(ON)
improves heavy load efficiency at the expense of
additional gate charge (usually) and more cost (usually).
Proper choice of MOSFET R
DS(ON)
becomes a trade-off
between tolerable efficiency loss, power dissipation and
cost. Note that while the lost power has a significant effect
on system efficiency, it only adds up to a watt or two in a
typical LTC1702 circuit, allowing the use of small, surface
mount MOSFETs without heat sinks.
Gate Charge
Gate charge is amount of charge (essentially, the number
of electrons) that the LTC1702 needs to put into the gate
of an external MOSFET to turn it on. The easiest way to
visualize gate charge is to think of it as a capacitance from
the gate pin of the MOSFET to SW (for QT) or to PGND (for
QB). This capacitance is composed of MOSFET channel
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LTC1702ACGN 功能描述:IC REG CTRLR BUCK PWM VM 24-SSOP RoHS:否 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:PolyPhase® 標(biāo)準(zhǔn)包裝:4,500 系列:PowerWise® PWM 型:控制器 輸出數(shù):1 頻率 - 最大:1MHz 占空比:95% 電源電壓:2.8 V ~ 5.5 V 降壓:是 升壓:無(wú) 回掃:無(wú) 反相:無(wú) 倍增器:無(wú) 除法器:無(wú) Cuk:無(wú) 隔離:無(wú) 工作溫度:-40°C ~ 125°C 封裝/外殼:6-WDFN 裸露焊盤 包裝:帶卷 (TR) 配用:LM1771EVAL-ND - BOARD EVALUATION LM1771 其它名稱:LM1771SSDX
LTC1702ACGN#PBF 功能描述:IC REG CTRLR BUCK PWM VM 24-SSOP RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:PolyPhase® 標(biāo)準(zhǔn)包裝:4,500 系列:PowerWise® PWM 型:控制器 輸出數(shù):1 頻率 - 最大:1MHz 占空比:95% 電源電壓:2.8 V ~ 5.5 V 降壓:是 升壓:無(wú) 回掃:無(wú) 反相:無(wú) 倍增器:無(wú) 除法器:無(wú) Cuk:無(wú) 隔離:無(wú) 工作溫度:-40°C ~ 125°C 封裝/外殼:6-WDFN 裸露焊盤 包裝:帶卷 (TR) 配用:LM1771EVAL-ND - BOARD EVALUATION LM1771 其它名稱:LM1771SSDX
LTC1702ACGN#TR 功能描述:IC REG CTRLR BUCK PWM VM 24-SSOP RoHS:否 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:PolyPhase® 標(biāo)準(zhǔn)包裝:4,500 系列:PowerWise® PWM 型:控制器 輸出數(shù):1 頻率 - 最大:1MHz 占空比:95% 電源電壓:2.8 V ~ 5.5 V 降壓:是 升壓:無(wú) 回掃:無(wú) 反相:無(wú) 倍增器:無(wú) 除法器:無(wú) Cuk:無(wú) 隔離:無(wú) 工作溫度:-40°C ~ 125°C 封裝/外殼:6-WDFN 裸露焊盤 包裝:帶卷 (TR) 配用:LM1771EVAL-ND - BOARD EVALUATION LM1771 其它名稱:LM1771SSDX
LTC1702ACGN#TRPBF 功能描述:IC REG CTRLR BUCK PWM VM 24-SSOP RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:PolyPhase® 標(biāo)準(zhǔn)包裝:4,500 系列:PowerWise® PWM 型:控制器 輸出數(shù):1 頻率 - 最大:1MHz 占空比:95% 電源電壓:2.8 V ~ 5.5 V 降壓:是 升壓:無(wú) 回掃:無(wú) 反相:無(wú) 倍增器:無(wú) 除法器:無(wú) Cuk:無(wú) 隔離:無(wú) 工作溫度:-40°C ~ 125°C 封裝/外殼:6-WDFN 裸露焊盤 包裝:帶卷 (TR) 配用:LM1771EVAL-ND - BOARD EVALUATION LM1771 其它名稱:LM1771SSDX
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