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參數(shù)資料
| 型號(hào)： | LTC1702I |
| 廠商： | Linear Technology Corporation |
| 元件分類： | 通用總線功能 |
| 英文描述： | Synchronous 8-Bit Up/Down Binary Counters 24-SOIC 0 to 70 |
| 中文描述： | 雙550kHz的同步二相開(kāi)關(guān)穩(wěn)壓器控制器 |
| 文件頁(yè)數(shù)： | 30/36頁(yè) |
| 文件大?。?/td> | 350K |
| 代理商： | LTC1702I |
30
LTC1702
APPLICATIO
S I
FOR
ATIO
U
Making L smaller than this optimum value yields little or no
improvement in transient response. As the output voltage
recovers, the inductor current will briefly rise above the
level of the output current to replenish the charge lost from
the output capacitor. With a properly compensated loop,
the entire recovery time will be inside of 10
μ
s.
Most loads care only about the maximum deviation from
ideal, which occurs somewhere in the first two cycles after
the load step hits. During this time, the output capacitor
does all the work until the inductor and control loop regain
control. The initial drop (or rise if the load steps down) is
entirely controlled by the ESR of the capacitor and amounts
to most of the total voltage drop. To minimize this drop,
reduce the ESR as much as possible by choosing low ESR
capacitors and/or paralleling multiple capacitors at the
output. The capacitance value accounts for the rest of the
voltage drop until the inductor current rises. With most
output capacitors, several devices paralleled to get the
ESR down will have so much capacitance that this drop
term is negligible. Ceramic capacitors are an exception; a
small ceramic capacitor can have suitably low ESR with
relatively small values of capacitance, making this second
drop term significant.
W
U
U
Optimizing Loop Compensation
Loop compensation has a fundamental impact on tran-
sient recovery time, the time it takes the LTC1702 to
recover after the output voltage has dropped due to output
capacitor ESR. Optimizing loop compensation entails
maintaining the highest possible loop bandwidth while
ensuring loop stability. The Feedback Component Selec-
tion section describes in detail how to design an optimized
feedback loop, appropriate for most LTC1702 systems.
Voltage Positioning
If the load transients consist primarily of load steps from
near zero load to full load and back, the transient response
can be traded off against DC regulation performance by
using a technique known as “voltage positioning.” The
goal is to intentionally compromise the DC regulation loop
such that the output rides near the maximum allowable
value (often +5%) with no load and near the minimum
allowable value at maximum load. With the load at zero,
any transient that comes along will be a current increase
which will cause the output voltage to fall. Since the output
voltage is initially at a high value, it can fall further before
LTC1702
FB
1702 F17a
1702 F17b
V
OUT
V
IN
+5%
NOM
–5%
MAX
0
V
OUT
LOAD
CURRENT
MAXIMUM
ALLOWABLE
TRANSIENT
Figure 17a. Standard Regulator
Figure 17b. Standard Regulator—Transient Response
LTC1702
FB
1702 F17c
1702 F17d
V
OUT
V
IN
+5%
NOM
–5%
MAX
0
V
OUT
LOAD
CURRENT
Figure 17c. Voltage Positioning Regulator
Figure 17d. Positioning Regulator—Transient Response
MAXIMUM
ALLOWABLE
TRANSIENT
≈
2
×
FIGURE 17b
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