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參數(shù)資料
| 型號： | LTC1741 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | 14-Bit, 80Msps Low Power 3V ADC |
| 中文描述： | 14位，80Msps ADC的低功耗3V的 |
| 文件頁數(shù)： | 13/20頁 |
| 文件大?。?/td> | 464K |
| 代理商： | LTC1741 |
LTC2249
13
2249f
APPLICATIOU
W
U
U
The noise performance of the LTC2249 can depend on the
clock signal quality as much as on the analog input. Any
noise present on the clock signal will result in additional
aperture jitter that will be RMS summed with the inherent
ADC aperture jitter.
In applications where jitter is critical, such as when digitiz-
ing high input frequencies, use as large an amplitude as
possible. Also, if the ADC is clocked with a sinusoidal
signal, filter the CLK signal to reduce wideband noise and
distortion products generated by the source.
Maximum and Minimum Conversion Rates
The maximum conversion rate for the LTC2249 is 80Msps.
For the ADC to operate properly, the CLK signal should
have a 50% (
±
5%) duty cycle. Each half cycle must have
at least 5.9ns for the ADC internal circuitry to have enough
settling time for proper operation.
An optional clock duty cycle stabilizer circuit can be used
if the input clock has a non 50% duty cycle. This circuit
uses the rising edge of the CLK pin to sample the analog
input. The falling edge of CLK is ignored and the internal
falling edge is generated by a phase-locked loop. The input
clock duty cycle can vary from 40% to 60% and the clock
duty cycle stabilizer will maintain a constant 50% internal
duty cycle. If the clock is turned off for a long period of
time, the duty cycle stabilizer circuit will require a hundred
clock cycles for the PLL to lock onto the input clock. To use
the clock duty cycle stabilizer, the MODE pin should be
connected to 1/3V
DD
or 2/3V
DD
using external resistors.
Input Range
The input range can be set based on the application. The
2V input range will provide the best signal-to-noise perfor-
mance while maintaining excellent SFDR. The 1V input
range will have better SFDR performance, but the SNR will
degrade by 5.7dB. See the Typical Performance Charac-
teristics section.
Driving the Clock Input
The CLK input can be driven directly with a CMOS or TTL
level signal. A sinusoidal clock can also be used along with
a low-jitter squaring circuit before the CLK pin (see
Figure 11).
V
CM
REFH
SENSE
TIE TO V
DD
FOR 2V RANGE;
TIE TO V
FOR 1V RANGE;
RANGE = 2 V
SENSE
FOR
0.5V < V
SENSE
< 1V
1.5V
REFL
2.2
μ
F
2.2
μ
F
INTERNAL ADC
HIGH REFERENCE
BUFFER
0.1
μ
F
2249 F09
LTC2249
4
DIFF AMP
1
μ
F
1
μ
F
INTERNAL ADC
LOW REFERENCE
1.5V BANDGAP
REFERENCE
1V
0.5V
RANGE
DETECT
AND
CONTROL
Figure 9. Equivalent Reference Circuit
V
CM
SENSE
1.5V
0.75V
2.2
μ
F
12k
1
μ
F
12k
2249 F10
LTC2249
Figure 10. 1.5V Range ADC
CLK
50
0.1
μ
F
0.1
μ
F
4.7
μ
F
1k
1k
FERRITE
BEAD
CLEAN
SUPPLY
SINUSOIDAL
CLOCK
INPUT
2249 F11
NC7SVU04
LTC2249
Figure 11. Sinusoidal Single-Ended CLK Drive
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