參數(shù)資料
型號(hào): LTC1742CFW#PBF
廠(chǎng)商: Linear Technology
文件頁(yè)數(shù): 7/20頁(yè)
文件大?。?/td> 0K
描述: IC ADC 14BIT 65MSPS 48-TSSOP
標(biāo)準(zhǔn)包裝: 39
位數(shù): 14
采樣率(每秒): 65M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 1.38W
電壓電源: 單電源
工作溫度: 0°C ~ 70°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 48-TFSOP(0.240",6.10mm 寬)
供應(yīng)商設(shè)備封裝: 48-TSSOP
包裝: 管件
輸入數(shù)目和類(lèi)型: 2 個(gè)單端,雙極;1 個(gè)差分,雙極
15
LTC1742
1742f
Any noise present on the encode signal will result in
additional aperture jitter that will be RMS summed with the
inherent ADC aperture jitter.
In applications where jitter is critical (high input frequen-
cies) take the following into consideration:
1. Differential drive should be used.
2. Use as large an amplitude as possible; if transformer
coupled use a higher turns ratio to increase the
amplitude.
3. If the ADC is clocked with a sinusoidal signal, filter the
encode signal to reduce wideband noise.
4. Balance the capacitance and series resistance at both
encode inputs so that any coupled noise will appear at
both inputs as common mode noise.
APPLICATIO S I FOR ATIO
WU
UU
VDD
LTC1742
1742 F07
BIAS
VDD
5V
ENC
ANALOG INPUT
2V BIAS
1:4
0.1
F
CLOCK
INPUT
50
6k
TO INTERNAL
ADC CIRCUITS
Figure 7. Transformer Driven ENC/ENC
1742 F08a
ENC
2V
VTHRESHOLD = 2V
ENC
0.1
F
LTC1742
1742 F08b
ENC
130
3.3V
130
D0
Q0
MC100LVELT22
LTC1742
83
83
Figure 8a. Single-Ended ENC Drive,
Not Recommended for Low Jitter
Figure 8b. ENC Drive Using a CMOS-to-PECL Translator
The encode inputs have a common mode range of 1.8V to
VDD. Each input may be driven from ground to VDD for
single-ended drive.
Maximum and Minimum Encode Rates
The maximum encode rate for the LTC1742 is 65Msps. For
the ADC to operate properly the encode signal should have
a 50% (
±5%) duty cycle. Each half cycle must have at least
7.3ns for the ADC internal circuitry to have enough settling
time for proper operation. Achieving a precise 50% duty
cycle is easy with differential sinusoidal drive using a
transformer or using symmetric differential logic such as
PECL or LVDS. When using a single-ended encode signal
asymmetric rise and fall times can result in duty cycles that
are far from 50%.
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