參數(shù)資料
型號: LTC1744CFW#TR
廠商: Linear Technology
文件頁數(shù): 1/24頁
文件大?。?/td> 0K
描述: IC ADC 14BIT 50MSPS 48-TSSOP
標(biāo)準(zhǔn)包裝: 1,800
位數(shù): 14
采樣率(每秒): 50M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 1.5W
電壓電源: 單電源
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 48-TFSOP(0.240",6.10mm 寬)
供應(yīng)商設(shè)備封裝: 48-TSSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 2 個單端,雙極;1 個差分,雙極
其它名稱: LTC1744CFWTR
1
LTC1744
1744f
14-Bit, 50Msps ADC
s
Sample Rate: 50Msps
s
77dB SNR and 87dB SFDR (3.2V Range)
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73.5dB SNR and 90dB SFDR (2V Range)
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No Missing Codes
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Single 5V Supply
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Power Dissipation: 1.2W
s
Selectable Input Ranges:
±1V or ±1.6V
s
150MHz Full Power Bandwidth S/H
s
Pin Compatible Family
25Msps: LTC1746 (14 Bit), LTC1745 (12 Bit)
50Msps: LTC1744 (14 Bit), LTC1743 (12 Bit)
65Msps: LTC1742 (14 Bit), LTC1741 (12 Bit)
80Msps: LTC1748 (14 Bit), LTC1747 (12 Bit)
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48-Pin TSSOP Package
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Telecommunications
s
Receivers
s
Base Stations
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Spectrum Analysis
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Imaging Systems
, LTC and LT are registered trademarks of Linear Technology Corporation.
OF
14-BIT
PIPELINED ADC
14
S/H
CIRCUIT
±1V
DIFFERENTIAL
ANALOG INPUT
AIN
+
AIN
SENSE
VCM
4.7
F
DIFF AMP
REFLA
REFHB
GND
1744 BD
ENC
4.7
F
0.1
F
0.1
F
1
F1F
REFHA
REFLB
BUFFER
RANGE
SELECT
2.5VREF
CORRECTION
LOGIC AND
SHIFT
REGISTER
OUTPUT
LATCHES
CONTROL LOGIC
OVDD
VDD
OGND
0.5V TO 5V
5V
0.1
F
1
F
1
F
1
F
D13
D0
CLKOUT
ENC
DIFFERENTIAL
ENCODE INPUT
OE
MSBINV
0.1
F
The LTC
1744 is a 50Msps, sampling 14-bit A/D con-
verter designed for digitizing high frequency, wide dynamic
range signals. Pin selectable input ranges of
±1Vand±1.6V
along with a resistor programmable mode allow the
LTC1744’s input range to be optimized for a wide variety
of applications.
The LTC1744 is perfect for demanding communications
applications with AC performance that includes 77dB
SNR and 87dB spurious free dynamic range. Ultralow jitter
of 0.3psRMS allows undersampling of IF frequencies with
excellent noise performance. DC specs include
±4LSB
maximum INL and no missing codes over temperature.
The digital interface is compatible with 5V, 3V and 2V logic
systems. The ENC and ENC inputs may be driven differen-
tially from PECL, GTL and other low swing logic families or
from single-ended TTL or CMOS. The low noise, high gain
ENC and ENC inputs may also be driven by a sinusoidal
signal without degrading performance. A separate output
power supply can be operated from 0.5V to 5V, making it
easy to connect directly to any low voltage DSPs or FIFOs.
The TSSOP package with a flow-through pinout simplifies
the board layout.
50Msps, 14-Bit ADC with a
±1V Differential Input Range
DESCRIPTIO
U
FEATURES
APPLICATIO S
U
BLOCK DIAGRA
W
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