fSAMPLE(MAX) Maximum Sampling Frequency q" />
參數(shù)資料
型號： LTC1744IFW
廠商： Linear Technology
文件頁數(shù)： 19/24頁
文件大?。?/td> 0K
描述： IC ADC 14BIT 50MSPS 48-TSSOP
標準包裝： 39
位數(shù)： 14
采樣率（每秒）： 50M
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 1.5W
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-TFSOP（0.240"，6.10mm 寬）
供應商設備封裝： 48-TSSOP
包裝： 管件
輸入數(shù)目和類型： 2 個單端，雙極；1 個差分，雙極
4
LTC1744
1744f
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
fSAMPLE(MAX)
Maximum Sampling Frequency
q
50
MHz
t1
ENC Low Time
(Note 9)
q
9.5
10
1000
ns
t2
ENC High Time
(Note 9)
q
9.5
10
1000
ns
t3
Aperture Delay of Sample-and-Hold
0
ns
t4
ENC to Data Delay
CL = 10pF (Note 8)
q
1.4
4.5
8
ns
t5
ENC to CLKOUT Delay
CL = 10pF (Note 8)
q
0.5
2.3
5
ns
t6
CLKOUT to Data Delay
CL = 10pF (Note 8)
q
0
2.2
ns
t7
DATA Access Time After OE
↓
CL = 10pF (Note 8)
10
25
ns
t8
BUS Relinquish Time
(Note 8)
10
25
ns
Data Latency
5
cycles
The q indicates specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
TI I G CHARACTERISTICS
U
W
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with GND
(unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: When these pin voltages are taken below GND, they will be
clamped by internal diodes. This product can handle input currents of
>100mA below GND without latchup. These pins are not clamped to VDD.
Note 5: VDD = 5V, fSAMPLE = 50MHz, differential ENC/ENC = 2VP-P 50MHz
sine wave, input range =
±1.6V differential, unless otherwise specified.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: Bipolar offset is the offset voltage measured from – 0.5 LSB
when the output code flickers between 00 0000 0000 0000 and 11
1111 1111 1111.
Note 8: Guaranteed by design, not subject to test.
Note 9: Recommended operating conditions.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VDD
Positive Supply Voltage
4.75
5.25
V
IDD
Positive Supply Current
q
245
300
mA
PDIS
Power Dissipation
q
1.2
1.5
W
OVDD
Digital Output Supply Voltage
0.5
VDD
V
The q indicates specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
POWER REQUIRE E TS
W
U
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VIH
High Level Input Voltage
VDD = 5.25V
q
2.4
V
VIL
Low Level Input Voltage
VDD = 4.75V
q
0.8
V
IIN
Digital Input Current
VIN = 0V to VDD
q
±10
A
CIN
Digital Input Capacitance
MSBINV and OE Only
1.5
pF
VOH
High Level Output Voltage
OVDD = 4.75V
IO = –10A
4.74
V
IO = – 200A
q
4V
VOL
Low Level Output Voltage
OVDD = 4.75V
IO = 160A
0.05
V
IO = 1.6mA
q
0.1
0.4
V
IOZ
Hi-Z Output Leakage D13 to D0
VOUT = 0V to VDD, OE = High
q
±10
A
COZ
Hi-Z Output Capacitance D13 to D0
OE = High (Note 8)
q
15
pF
ISOURCE
Output Source Current
VOUT = 0V
– 50
mA
ISINK
Output Sink Current
VOUT = 5V
50
mA
The q indicates specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
DIGITAL I PUTS A D DIGITAL OUTPUTS
U
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