參數(shù)資料
型號(hào): LTC1749IFW
廠商: Linear Technology
文件頁(yè)數(shù): 8/20頁(yè)
文件大?。?/td> 0K
描述: IC ADC 12BIT 80MSPS SMPL 48TSSOP
標(biāo)準(zhǔn)包裝: 39
位數(shù): 12
采樣率(每秒): 80M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 1.69W
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-TFSOP(0.240",6.10mm 寬)
供應(yīng)商設(shè)備封裝: 48-TSSOP
包裝: 管件
輸入數(shù)目和類型: 2 個(gè)單端,雙極;1 個(gè)差分,雙極
16
LTC1749
1749f
Maximum and Minimum Encode Rates
The maximum encode rate for the LTC1749 is 80Msps. For
the ADC to operate properly the encode signal should have
a 50% (
±4%) duty cycle. Each half cycle must have at least
6ns for the ADC internal circuitry to have enough settling
time for proper operation. Achieving a precise 50% duty
cycle is easy with differential sinusoidal drive using a
transformer or using symmetric differential logic such as
PECL or LVDS. When using a single-ended encode signal
asymmetric rise and fall times can result in duty cycles that
are far from 50%.
At sample rates slower than 80Msps the duty cycle can
vary from 50% as long as each half cycle is at least 6ns.
The lower limit of the LTC1749 sample rate is determined
by droop of the sample-and-hold circuits. The pipelined
APPLICATIO S I FOR ATIO
WU
UU
architecture of this ADC relies on storing analog signals on
small valued capacitors. Junction leakage will discharge
the capacitors. The specified minimum operating fre-
quency for the LTC1749 is 1Msps.
DIGITAL OUTPUTS
Digital Output Buffers
Figure 9 shows an equivalent circuit for a single output
buffer. Each buffer is powered by OVDD and OGND, iso-
lated from the ADC power and ground. The additional
N-channel transistor in the output driver allows operation
down to low voltages. The internal resistor in series with
the output makes the output appear as 50
to external
circuitry and may eliminate the need for external damping
resistors.
Figure 7. Transformer Driven ENC/ENC
Figure 8a. Single-Ended ENC Drive,
Not Recommended for Low Jitter
Figure 8b. ENC Drive Using a CMOS-to-PECL Translator
VDD
LTC1749
1749 F07
BIAS
VDD
5V
ENC
ANALOG INPUT
2V BIAS
1:4
0.1
F
CLOCK
INPUT
50
6k
TO INTERNAL
ADC CIRCUITS
1749 F08a
ENC
2V
VTHRESHOLD = 2V
ENC
0.1
F
LTC1749
1749 F08b
ENC
130
3.3V
130
D0
Q0
MC100LVELT22
LTC1749
83
83
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