參數(shù)資料
型號: LTC1750CFW#TRPBF
廠商: Linear Technology
文件頁數(shù): 10/20頁
文件大小: 0K
描述: IC ADC 14BIT 80MSPS SMPL 48TSSOP
標準包裝: 1,800
位數(shù): 14
采樣率(每秒): 80M
數(shù)據(jù)接口: 并聯(lián)
轉換器數(shù)目: 1
功率耗散(最大): 1.69W
電壓電源: 單電源
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 48-TFSOP(0.240",6.10mm 寬)
供應商設備封裝: 48-TSSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 2 個單端,雙極;1 個差分,雙極
18
LTC1750
1750f
REFLA. These capacitors should be as close to the device
as possible (1.5mm or less). Size 0402 ceramic capacitors
are recomended. The large 4.7
FcapacitorbetweenREFHA
and REFLA can be somewhat further away. The traces
connecting the pins and bypass capacitors must be kept
short and should be made as wide as possible.
The LTC1750 differential inputs should run parallel and
close to each other. The input traces should be as short as
possible to minimize capacitance and to minimize noise
pickup.
An analog ground plane separate from the digital process-
ing system ground should be used. All ADC ground pins
labeled GND should connect to this plane. All ADC VDD
bypass capacitors, reference bypass capacitors and input
filter capacitors should connect to this analog plane. The
LTC1750 has three output driver ground pins, labeled
OGND (Pins 27, 38 and 47). These grounds should con-
nect to the digital processing system ground. The output
driver supply, OVDD should be connected to the digital
processing system supply. OVDD bypasscapacitorsshould
bypass to the digital system ground. The digital process-
ing system ground should be connected to the analog
plane at ADC OGND (Pin 38).
HEAT TRANSFER
Most of the heat generated by the LTC1750 is transferred
from the die through the package leads onto the printed
circuit board. In particular, ground pins 12, 13, 36 and 37
are fused to the die attach pad. These pins have the lowest
thermal resistance between the die and the outside envi-
ronment. It is critical that all ground pins are connected to
a ground plane of sufficient area. The layout of the evalu-
ation circuit shown on the following pages has a low ther-
mal resistance path to the internal ground plane by using
multiple vias near the ground pins. A ground plane of this
size results in a thermal resistance from the die to ambient
of 35
°C/W.Smallerareagroundplanesorpoorlyconnected
ground pins will result in higher thermal resistance.
APPLICATIO S I FOR ATIO
WU
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