參數(shù)資料
型號(hào): LTC1772B
廠商: Linear Technology Corporation
英文描述: Constant Frequency Current Mode Step-Down DC/DC Controller in SOT-23
中文描述: 恒定頻率電流模式降壓DC / DC控制器,采用SOT - 23
文件頁(yè)數(shù): 10/12頁(yè)
文件大?。?/td> 196K
代理商: LTC1772B
10
LTC1772B
APPLICATIO
S I
N
FOR
ATIO
U
Foldback Current Limiting
As described in the Output Diode Selection, the worst-case
dissipation occurs with a short-circuited output when the
diode conducts the current limit value almost continu-
ously. To prevent excessive heating in the diode, foldback
current limiting can be added to reduce the current in
proportion to the severity of the fault.
Foldback current limiting is implemented by adding diodes
D
FB1
and D
FB2
between the output and the I
TH
/RUN pin as
shown in Figure 6. In a hard short (V
OUT
= 0V), the current
will be reduced to approximately 50% of the maximum
output current.
W
U
V
FB
I
TH
/RUN
V
OUT
LTC1772B
R1
1772 F05
R2
D
FB1
D
FB2
+
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
Figure 7. LTC1772B Layout Diagram (See PC Board Layout Checklist)
L1
M1
R1
BOLD LINES INDICATE HIGH CURRENT PATHS
R2
D1
R
SENSE
V
IN
V
OUT
1772 F06
0.1
μ
F
C
OUT
C
ITH
R
ITH
+
C
IN
+
I
TH
/RUN
LTC1772B
GND
V
FB
6
5
4
1
2
3
PGATE
V
IN
SENSE
LTC1772B. These items are illustrated graphically in the
layout diagram in Figure 7. Check the following in your
layout:
1. Is the Schottky diode closely connected between ground
(Pin 2) and drain of the external MOSFET
2. Does the (+) plate of C
IN
connect to the sense resistor
as closely as possible This capacitor provides AC
current to the MOSFET.
3. Is the input decoupling capacitor (0.1
μ
F) connected
closely between V
IN
(Pin 5) and ground (Pin 2)
4. Connect the end of R
SENSE
as close to V
IN
(Pin 5) as
possible. The V
IN
pin is the SENSE
+
of the current
comparator.
5. Is the trace from SENSE
(Pin 4) to the Sense resistor
kept short Does the trace connect close to R
SENSE
6. Keep the switching node PGATE away from sensitive
small signal nodes.
7. Does the V
FB
pin connect directly to the feedback
resistors The resistive divider R1 and R2 must be
connected between the (+) plate of C
OUT
and signal
ground.
Figure 6. Foldback Current Limiting
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