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參數(shù)資料
| 型號： | LTC1775I |
| 廠商： | Linear Technology Corporation |
| 英文描述： | Quadruple 2-Input Positive-NAND Gate 14-SOIC -40 to 85 |
| 中文描述： | 高功率無檢測電阻商標電流模式同步降壓型開關(guān)穩(wěn)壓器 |
| 文件頁數(shù)： | 17/24頁 |
| 文件大?。?/td> | 289K |
| 代理商： | LTC1775I |
17
LTC1775
losses ranging from 2% to 8% as the output current
increases from 0.5A to 2A for a 5V output. I
2
R losses
cause the efficiency to drop at high output currents.
3. Transition losses apply only to the topside MOSFET,
and only when operating at high input voltages (typi-
cally 20V or greater). Transition losses can be esti-
mated from:
Transition Loss = (1.7)(V
IN2
)(I
O(MAX)
)(C
RSS
)(f)
4. LTC1775 V
IN
supply current. The V
IN
current is the DC
supply current to the controller excluding MOSFET gate
drive current. Total supply current is typically about
850
μ
A. If EXTV
CC
is connected to 5V, the LTC1775 will
draw only 330
μ
A from V
IN
and the remaining 520
μ
A will
come from EXTV
CC
. V
IN
current results in a small
(<1%) loss which increases with V
IN
.
Other losses including C
IN
and C
OUT
ESR dissipative
losses, Schottky conduction losses during dead time and
inductor core losses, generally account for less than 2%
total additional loss.
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
OUT
immediately shifts by an amount
equal to (
I
LOAD
)(ESR), where ESR is the effective series
resistance of C
OUT
, and C
OUT
begins to charge or dis-
charge. The regulator loop acts on the resulting feedback
error signal to return V
OUT
to its steady-state value. During
this recovery time V
OUT
can be monitored for overshoot or
ringing which would indicate a stability problem. The I
TH
pin external components shown in Figure 1 will provide
adequate compensation for most applications.
A second, more severe transient is caused by connecting
loads with large (>1
μ
F) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C
OUT
, causing a rapid drop in V
OUT
. No regulator can
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive in order
to limit the inrush current to the load.
cycle skipping can occur with correspondingly larger
current and voltage ripple.
Efficiency Considerations
The efficiency of a switching regulator is equal to the
output power divided by the input power (
×
100%). Per-
cent efficiency can be expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage
of input power. It is often useful to analyze individual
losses to determine what is limiting the efficiency and
which change would produce the most improvement.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC1775 circuits:
1. INTV
CC
current. This is the sum of the MOSFET driver
and control currents. The driver current results from
switching the gate capacitance of the power MOSFETs.
Each time a MOSFET gate is switched on and then off,
a packet of gate charge Q
g
moves from INTV
CC
to
ground. The resulting current out of INTV
CC
is typically
much larger than the control circuit current. In continu-
ous mode, I
GATECHG
= f(Q
g(TOP)
+ Q
g(BOT)
).
By powering EXTV
CC
from an output-derived source,
the additional V
IN
current resulting from the driver and
control currents will be scaled by a factor of Duty Cycle/
Efficiency. For example, in a 20V to 5V application at
400mA load, 10mA of INTV
CC
current results in ap-
proximately 3mA of V
IN
current. This reduces the loss
from 10% (if the driver was powered directly from V
IN
)
to about 3%.
2. DC I
2
R Losses. Since there is no separate sense resis-
tor, DC I
2
R losses arise only from the resistances of the
MOSFETs and inductor. In continuous mode the aver-
age output current flows through L, but is “chopped”
between the top MOSFET and the bottom MOSFET. If
the two MOSFETs have approximately the same R
DS(ON)
,
then the resistance of one MOSFET can simply be
summed with the resistance of L to obtain the DC I
2
R
loss. For example, if each R
DS(ON)
= 0.05
and R
L
=
0.15
, then the total resistance is 0.2
. This results in
APPLICATIOU
W
U
U
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