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參數(shù)資料
| 型號： | LTC1821BIGW#TR |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 16/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC D/A CONV 16BIT PRECISE 36SSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 設(shè)置時間： | 2µs |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 36-BSOP（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 36-SSOP |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 1 電壓，單極；1 電壓，雙極 |
| 采樣率（每秒）： | * |
| 其它名稱： | LTC1821BIGWTR |
9
LTC1821
Description
The LTC1821 is a 16-bit voltage output DAC with a full
parallel 16-bit digital interface. The device can operate
from 5V and
±15 supplies and provides both unipolar 0V
to – 10V or 0V to 10V and bipolar
±10V output ranges from
a 10V or –10V reference input. Additionally, the power
supplies for the LTC1821 can go as low as 4.5V and
±4.5V.
In this case for a 2.5V or – 2.5V reference, the output range
is 0V to – 2.5V, 0V to 2.5V and
±2.5V. The LTC1821 has
three additional precision resistors on chip for bipolar
operation. Refer to the block diagram regarding the fol-
lowing description.
The 16-bit DAC consists of a precision R-2R ladder for the
13 LSBs. The three MSBs are decoded into seven seg-
ments of resistor value R. Each of these segments and the
R-2R ladder carries an equally weighted current of one
eighth of full scale. The feedback resistor RFB and
4-quadrant resistor ROFS have a value of R/4. 4-quadrant
resistors R1 and R2 have a magnitude of R/4. R1 and R2
together with an external op amp (see Figure 2) inverts the
reference input voltage and applies it to the 16-bit DAC
input REF, in 4-quadrant operation. The REF pin presents
a constant input impedance of R/8 in unipolar mode and
R/12 in bipolar mode.
The LTC1821 contains an onboard precision high speed
amplifier. This amplifier together with the feedback resis-
tor (RFB) form a precision current-to-voltage converter for
the DAC’s current output. The amplifier has very low noise,
offset, input bias current and settles in less than 2
s to
0.0015% for a 10V step. It can sink and source 22mA
(
±15V) typically and can drive a 300pF capacitive load. An
added feature of these devices, especially for waveform
generation, is a proprietary deglitcher that reduces glitch
impulse to below 2nV-s over the DAC output voltage range.
Digital Section
The LTC1821 has a 16-bit wide full parallel data bus input.
The device is double-buffered with two 16-bit registers.
The double-buffered feature permits the update of several
DACs simultaneously. The input register is loaded directly
from a 16-bit microprocessor bus when the WR pin is
brought to a logic low level. The second register (DAC
register) is updated with the data from the input register
when the LD signal is brought to a logic high. Updating the
DAC register updates the DAC output with the new data. To
make both registers transparent in flowthrough mode, tie
WR low and LD high. However, this defeats the deglitcher
operation and output glitch impulse may increase. The
deglitcher is activated on the rising edge of the LD pin. The
APPLICATIONS INFORMATION
WU
U
DATA
LD
CLR
1821 TD
tWR
tDS
tLD
tDH
tLWD
WR
tCLR
TI I G DIAGRA
U
WW
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