TIMING CHARACTERISTICS The l " />
參數(shù)資料
型號(hào)： LTC1859IG#PBF
廠商： Linear Technology
文件頁(yè)數(shù)： 16/20頁(yè)
文件大小： 0K
描述： IC A/D CONV 8CH 16BIT 28-SSOP
標(biāo)準(zhǔn)包裝： 47
系列： SoftSpan™
位數(shù)： 16
采樣率（每秒）： 100k
數(shù)據(jù)接口： MICROWIRE?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 40mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 28-SSOP（0.209"，5.30mm 寬）
供應(yīng)商設(shè)備封裝： 28-SSOP
包裝： 管件
輸入數(shù)目和類型： 8 個(gè)單端，單極；8 個(gè)單端，雙極；4 個(gè)差分，單極；4 個(gè)差分，雙極
配用： DC682A-ND - BOARD SAR ADC LTC1859
LTC1857/LTC1858/LTC1859
5
185789fa
TIMING CHARACTERISTICS The l denotes the specications which apply over the full operating temperature
range, otherwise specications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
fSAMPLE(MAX)
Maximum Sampling Frequency
Through CH0 to CH7 Inputs
Through ADC+, ADC– Only
l
100
166
kHz
tCONV
Conversion Time
l
45
μs
tACQ
Acquisition Time
Through CH0 to CH7 Inputs
Through ADC+, ADC– Only
l
1
4μs
μs
fSCK
SCK Frequency
(Note 14)
l
020
MHz
tr
SDO Rise Time
See Test Circuits
6
ns
tf
SDO Fall Time
See Test Circuits
6
ns
t1
CONVST High Time
l
40
ns
t2
CONVST to BUSY Delay
CL = 25pF, See Test Circuits
l
15
30
ns
t3
SCK Period
l
50
ns
t4
SCK High
l
10
ns
t5
SCK Low
l
10
ns
t6
Delay Time, SCK
↓ to SDO Valid
CL = 25pF, See Test Circuits
l
25
45
ns
t7
Time from Previous SDO Data Remains
Valid After SCK
↓
CL = 25pF, See Test Circuits
l
520
ns
t8
SDO Valid After RD
↓
CL = 25pF, See Test Circuits
l
11
30
ns
t9
RD↓ to SCK Setup Time
l
20
ns
t10
SDI Setup Time Before SCK
↑
l
0ns
t11
SDI Hold Time After SCK
↑
l
7ns
t12
SDO Valid Before BUSY
↑
RD = Low, CL = 25pF, See Test Circuits
l
520
ns
t13
Bus Relinquish Time
See Test Circuits
l
10
30
ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground with DGND, AGND1,
AGND2 and AGND3 wired together unless otherwise noted.
Note 3: When these pin voltages are taken below ground or above AVDD =
DVDD = OVDD = VDD, they will be clamped by internal diodes. This product
can handle currents of greater than 100mA below ground or above VDD
without latchup.
Note 4: When these pin voltages are taken below ground they will be
clamped by internal diodes. This product can handle currents of greater
than 100mA below ground without latchup. These pins are not clamped
to VDD.
Note 5: VDD = 5V, fSAMPLE = 100kHz, tr = tf = 5ns unless otherwise
specied.
Note 6: Linearity, offset and full-scale specications apply for a single-
ended analog MUX input with respect to ground or ADC+ with respect to
ADC– tied to ground.
Note 7: Integral nonlinearity is dened as the deviation of a code from a
straight line passing through the actual end points of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Bipolar zero error is the offset voltage measured from – 0.5LSB
when the output code ickers between 0000 0000 0000 0000 and 1111
1111 1111 1111 for the LTC1859, between 00 0000 0000 0000 and 11
1111 1111 1111 for the LTC1858 and between 0000 0000 0000 and
1111 1111 1111 for the LTC1857. Unipolar zero error is the offset voltage
measured from 0.5LSB when the output codes icker between 0000 0000
0000 0000 and 0000 0000 0000 0001 for the LTC1859, between 00 0000
0000 0000 and 00 0000 0000 0001 for the LTC1858 and between 0000
0000 0000 and 0000 0000 0001 for the LTC1857.
Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
Note 11: Full-scale bipolar error is the worst case of –FS or +FS
untrimmed deviation from ideal rst and last code transitions, divided by
the full-scale range, and includes the effect of offset error. For unipolar
full-scale error, the deviation of the last code transition from ideal, divided
by the full-scale range, and includes the effect of offset error.
Note 12: All Specications in dB are referred to a full-scale ±10V input.
Note 13: Recovers to specied performance after (2 FS) input
overvoltage.
Note 14: t6 of 45ns maximum allows fSCK up to 10MHz for rising capture
with 50% duty cycle and fSCK up to 20MHz for falling capture (with 5ns
setup time for the receiving logic).
Note 15: The specication is referred to the ±10V input range.
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