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參數(shù)資料
| 型號(hào)： | LTC1863CGN#PBF |
| 廠商： | Linear Technology |
| 文件頁(yè)數(shù)： | 4/16頁(yè) |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT 8CH 200KSPS 16SSOP |
| 標(biāo)準(zhǔn)包裝： | 100 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 200k |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 9mW |
| 電壓電源： | 單電源 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 8 個(gè)單端，單極；8 個(gè)單端，雙極；4 個(gè)差分，單極；4 個(gè)差分，雙極 |
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LTC1863/LTC1867
12
18637fa
APPLICATIONS INFORMATION
Digital Interface
The LTC1863/LTC1867 have very simple digital interface
that is enabled by the control input, CS/CONV. A logic
rising edge applied to the CS/CONV input will initiate a
conversion. After the conversion, taking CS/CONV low will
enable the serial port and the ADC will present digital data
in two’s complement format in bipolar mode or straight
binary format in unipolar mode, through the SCK/SDO
serial port.
Internal Clock
The internal clock is factory trimmed to achieve a typical
conversion time of 3μs and a maximum conversion time,
3.5μs, over the full operating temperature range. The typi-
cal acquisition time is 1.1μs, and a throughput sampling
rate of 200ksps is tested and guaranteed.
Automatic Nap Mode
The LTC1863/LTC1867 go into automatic nap mode when
CS/CONV is held high after the conversion is complete.
With a typical operating current of 1.3mA and automatic
150μA nap mode between conversions, the power dis-
sipation drops with reduced sample rate. The ADC only
keeps the VREF and REFCOMP voltages active when
the part is in the automatic nap mode. The slower the
sample rate allows the power dissipation to be lower (see
Figure 5).
R2
R3
REFERENCE
AMP
10μF
2.2μF
REFCOMP
GND
VREF
R1
6k
10
9
15
2.5V
4.096V
LTC1863/LTC1867
1867 F04a
BANDGAP
REFERENCE
10
0.1μF
10μF
1867 F04b
LT1019A-2.5
VOUT
VIN
5V
VREF
LTC1863/
LTC1867
GND
REFCOMP
15
9
+
2.2μF
Figure 4b. Using the LT1019-2.5 as an External Reference
Figure 4a. LT1867 Reference Circuit
fSAMPLE (ksps)
1
SUPPL
Y
CURRENT
(mA)
2.0
1.5
1.0
0.5
0
10
100
1000
18637 G10
VDD = 5V
Figure 5. Supply Current vs fSAMPLE
where V1 is the RMS amplitude of the fundamental
frequency and V2 through VN are the amplitudes of the
second through Nth harmonics.
Internal Reference
The LTC1863/LTC1867 has an on-chip, temperature
compensated, curvature corrected, bandgap reference
that is factory trimmed to 2.5V. It is internally connected
to a reference amplier and is available at VREF (Pin 10).
A 6k resistor is in series with the output so that it can be
easily overdriven by an external reference if better drift
and/or accuracy are required as shown in Figure 4. The
reference amplier gains the VREF voltage by 1.638V to
4.096V at REFCOMP (Pin 9). This reference amplier
compensation pin, REFCOMP, must be bypassed with a
10μF ceramic or tantalum in parallel with a 0.1μF ceramic
for best noise performance.
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