t5 (SDI Setup Time Before SCK↑),
參數(shù)資料
型號: LTC1867AIGN#TRPBF
廠商: Linear Technology
文件頁數(shù): 15/16頁
文件大?。?/td> 0K
描述: IC ADC 16BIT 8CH 200KSPS 16SSOP
標準包裝: 2,500
位數(shù): 16
采樣率(每秒): 200k
數(shù)據(jù)接口: MICROWIRE?,串行,SPI?
轉換器數(shù)目: 1
功率耗散(最大): 9mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-SSOP(0.154",3.90mm 寬)
供應商設備封裝: 16-SSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 8 個單端,單極;8 個單端,雙極;4 個差分,單極;4 個差分,雙極
配用: DC873A-ND - BOARD SAR ADC LTC1867L
DC806A-ND - BOARD SAR ADC LTC1867
LTC1863/LTC1867
8
18637fa
TIMING DIAGRAMS
t5 (SDI Setup Time Before SCK↑),
t6 (SDI Hold Time After SCK↑)
50%
t3
0.4V
t7 (SLEEP Mode Wake-Up Time)
t7
SCK
CS/CONV
t8 (BUS Relinquish Time)
t8
CS/CONV
SDO
2.4V
t4 (SDO Valid After CONV↓)
t4
CS/CONV
SDO
2.4V
0.4V
t6
2.4V
0.4V
t5
SCK
SDI
2.4V
0.4V
2.4V
0.4V
SDO
1867 TD
SLEEP BIT (SLP = 0)
READ-IN
10%
90%
Hi-Z
t1 (For Short Pulse Mode)
t2 (SDO Valid Before SCK↑),
t3 (SDO Valid Hold Time After SCK↓)
t1
CS/CONV
t2
SCK
50%
Overview
The LTC1863/LTC1867 are complete, low power multi-
plexed ADCs. They consist of a 12-/16-bit, 200ksps capaci-
tive successive approximation A/D converter, a precision
internal reference, a congurable 8-channel analog input
multiplexer (MUX) and a serial port for data transfer.
Conversions are started by a rising edge on the CS/CONV
input. Once a conversion cycle has begun, it cannot be
restarted. Between conversions, the ADCs receive an input
word for channel selection and output the conversion
result, and the analog input is acquired in preparation for
the next conversion. In the acquire phase, a minimum time
of 1.5μs will provide enough time for the sample-and-hold
capacitors to acquire the analog signal.
During the conversion, the internal differential 16-bit
capacitive DAC output is sequenced by the SAR from
the most signicant bit (MSB) to the least signicant bit
(LSB). The input is sucessively compared with the binary
weighted charges supplied by the differential capacitive
DAC. Bit decisions are made by a low-power, differential
comparator. At the end of a conversion, the DAC output
balances the analog input. The SAR contents (a 12-/16-bit
data word) that represent the analog input are loaded into
the 12-/16-bit output latches.
APPLICATIONS INFORMATION
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相關代理商/技術參數(shù)
參數(shù)描述
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