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參數(shù)資料
| 型號(hào)： | LTC2053CMS8-SYNC#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 2/18頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC INSTRUMNT AMP R-RIN/OUT 8MSOP |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 放大器類型： | 斷路器（零漂移） |
| 電路數(shù)： | 1 |
| 輸出類型： | 滿擺幅 |
| 轉(zhuǎn)換速率： | 0.2 V/µs |
| 增益帶寬積： | 200kHz |
| 電流 - 輸入偏壓： | 4nA |
| 電壓 - 輸入偏移： | 5µV |
| 電流 - 電源： | 950µA |
| 電壓 - 電源，單路/雙路(±)： | 2.7 V ~ 11 V，±1.35 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-MSOP |
| 包裝： | 管件 |
LTC2053/LTC2053-SYNC
0
2053syncfc
block DiagraM
–
+
ZERO-DRIFT
OP AMP
CH
OUT
2053 BD
4
V–
5
REF
6
RG
8
V+
1
EN/CLK*
3
+IN
2
–IN
CS
7
*NOTE: PIN 1 IS EN ON THE LTC2053 AND CLK ON THE LTC2053-SYNC
applicaTions inForMaTion
Theory of Operation
The LTC2053 uses an internal capacitor (CS) to sample
a differential input signal riding on a DC common mode
voltage (see the Block Diagram). This capacitor’s charge is
transferred to a second internal hold capacitor (CH) trans-
lating the common mode of the input differential signal to
that of the REF pin. The resulting signal is amplified by a
zero-drift op amp in the noninverting configuration. The
RG pin is the negative input of this op amp and allows
external programmability of the DC gain. Simple filtering
can be realized by using an external capacitor across the
feedback resistor.
Input Voltage Range
The input common mode voltage range of the LTC2053
is rail-to-rail. However, the following equation limits the
size of the differential input voltage:
V– ≤ (V+IN – V–IN) + VREF ≤ V+ – 1.3
Where V+IN and V–IN are the voltages of the +IN and –IN
pins, respectively, VREF is the voltage at the REF pin and
V+ is the positive supply voltage.
For example, with a 3V single supply and a 0V to 100mV
differential input voltage, VREF must be between 0V and
1.6V.
±5 Volt Operation
When using the LTC2053 with supplies over 5.5V, care
must be taken to limit the maximum difference between
any of the input pins (+IN or –IN) and the REF pin to
5.5V; if not, the device will be damaged. For example, if
rail-to-rail input operation is desired when the supplies
are at ±5V, the REF pin should be 0V, ±0.5V. As a second
example, if V+ is 10V and V– and REF are at 0V, the inputs
should not exceed 5.5V.
Settling Time
The sampling rate is 3kHz and the input sampling period
during which CS is charged to the input differential voltage
VIN is approximately 150s. First assume that on each
input sampling period, CS is charged fully to VIN. Since
CS = CH (= 1000pF), a change in the input will settle to
N bits of accuracy at the op amp noninverting input after
N clock cycles or 333s(N). The settling time at the OUT
pin is also affected by the settling of the internal op amp.
Since the gain bandwidth of the internal op amp is typically
200kHz, the settling time is dominated by the switched
capacitor front end for gains below 100 (see the Typical
Performance Characteristics section).
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