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參數(shù)資料
| 型號： | LTC2053HDD |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 運動控制電子 |
| 英文描述： | Precision Instrumentation Amplifier |
| 中文描述： | INSTRUMENTATION AMPLIFIER, 20 uV OFFSET-MAX, PDSO8 |
| 封裝： | 3 X 3 MM, 0.80 MM HEIGHT, PLASTIC, DFN-8 |
| 文件頁數(shù)： | 10/12頁 |
| 文件大?。?/td> | 288K |
| 代理商： | LTC2053HDD |
LTC2053
10
2053fa
APPLICATIU
Settling Time
The sampling rate is 3kHz and the input sampling period
during which C
S
is charged to the input differential voltage
V
IN
is approximately 150
μ
s. First assume that on each
input sampling period, C
S
is charged fully to V
IN
. Since C
S
= C
H
(= 1000pF), a change in the input will settle to N bits
of accuracy at the op amp noninverting input after N clock
cycles or 333
μ
s(N). The settling time at the OUT pin is also
affected by the settling of the internal op amp. Since the
gain bandwidth of the internal op amp is typically 200kHz,
the settling time is dominated by the switched capacitor
front end for gains below 100 (see Typical Performance
Characteristics).
W
U
U
charging current decays exponentially during each input
sampling period with a time constant equal to R
S
C
S
.
If the
voltage disturbance due to these currents settles before
the end of the sampling period, there will be no errors
due to source resistance or the source resistance mis-
match between –IN and +IN. With R
S
less than 10k, no
DC errors occur due to this input current.
In the Typical Performance Characteristics section of this
data sheet, there are curves showing the additional error
from non-zero source resistance in the inputs. If there are
no large capacitors across the inputs, the amplifier is less
sensitive to source resistance and source resistance mis-
match. When large capacitors are placed across the in-
puts, the input charging currents described above result in
larger DC errors, especially with source resistor mis-
matches.
Power Supply Bypassing
The LTC2053 uses a sampled data technique and therefore
contains some clocked digital circuitry. It is therefore
sensistive to supply bypassing. For single or dual supply
operation, a 0.1
μ
F ceramic capacitor must be connected
between Pin 8 (V
+
) and Pin 4 (V
–
) with leads as short as
possible.
–
+
–
+
V
D
V
+IN
V
OUT
V
–IN
3
8
5V
4
5
6
7
2
–
+
–
+
V
D
V
+IN
V
OUT
V
–IN
V
REF
–5V
3
2053 F01
8
5V
0V < V
+IN
< 5V
0V < V
–IN
< 5V
0V < V
D
< 3.7V
V
OUT
= V
D
–5V < V
–IN
< 5V AND
V
–IN
– V
REF
< 5.5V
–5V < V
+IN
< 5V AND
V
+IN
– V
REF
< 5.5V
–5V < V
D
+ V
REF
< 3.7V
R2
R1
SINGLE SUPPLY, UNITY GAIN
DUAL SUPPLY
4
5
6R2
R1
7
2
V
OUT
= 1 +
V
D
+ V
REF
(
Input Current
Whenever the differential input V
IN
changes, C
H
must be
charged up to the new input voltage via C
S
. This results in
an input charging current during each input sampling
period. Eventually, C
H
and C
S
will reach V
IN
and, ideally,
the input current would go to zero for DC inputs.
In reality, there are additional parasitic capacitors which
disturb the charge on C
S
every cycle even if V
IN
is a DC
voltage. For example, the parasitic bottom plate capacitor
on C
S
must be charged from the voltage on the REF pin to
the voltage on the –IN pin every cycle. The resulting input
Figure 1
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