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參數(shù)資料
| 型號： | LTC2145IUP-14#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 6/38頁 |
| 文件大小： | 0K |
| 描述： | IC ADC DUAL 14BIT 125MSPS 64-QFN |
| 標準包裝： | 40 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 125M |
| 數(shù)據(jù)接口： | 并聯(lián)，串行，SPI |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 360mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-WFQFN 裸露焊盤 |
| 供應商設備封裝： | 64-QFN（9x9） |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 2 個差分 |
| 配用： | DC890B-ND - BOARD USB DATA COLLECTION |
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LTC2145-14/
LTC2144-14/LTC2143-14
14
21454314fa
PINS THAT ARE THE SAME FOR ALL DIGITAL
OUTPUT MODES
VDD (Pins 1, 16, 17, 64): Analog Power Supply, 1.7V to
1.9V. Bypass to ground with 0.1μF ceramic capacitors.
Adjacent pins can share a bypass capacitor.
VCM1 (Pin 2):Common Mode Bias Output, Nominally Equal
to VDD/2. VCM1 should be used to bias the common mode
of the analog inputs to channel 1. Bypass to ground with
a 0.1μF ceramic capacitor.
GND (Pins 3, 6, 14): ADC Power Ground.
AIN1+ (Pin 4): Channel 1 Positive Differential Analog Input.
AIN1– (Pin 5): Channel 1 Negative Differential Analog Input.
REFH (Pins 7, 9): ADC High Reference. See the Applica-
tions Information section for recommended bypassing
circuits for REFH and REFL.
REFL (Pins 8, 10): ADC Low Reference. See the Applica-
tions Information section for recommended bypassing
circuits for REFH and REFL.
PAR/SER (Pin 11): Programming Mode Selection Pin.
Connect to ground to enable the serial programming mode.
CS, SCK, SDI, SDO become a serial interface that control
the A/D operating modes. Connect to VDD to enable the
parallel programming mode where CS, SCK, SDI, SDO
become parallel logic inputs that control a reduced set of
the A/D operating modes. PAR/SER should be connected
directly to ground or VDD and not be driven by a logic signal.
AIN2+(Pin12):Channel2PositiveDifferentialAnalogInput.
AIN2–(Pin13):Channel2NegativeDifferentialAnalogInput.
VCM2 (Pin 15): Common Mode Bias Output, Nominally
Equal to VDD/2. VCM2 should be used to bias the common
mode of the analog inputs to channel 2. Bypass to ground
with a 0.1μF ceramic capacitor.
ENC+ (Pin 18):
Encode Input. Conversion starts on the
rising edge.
ENC– (Pin 19):
Encode Complement Input. Conversion
starts on the falling edge. Tie to GND for single-ended
encode mode.
CS (Pin 20): In Serial Programming Mode, (PAR/SER =
0V), CS Is the Serial Interface Chip Select Input. When
CS is low, SCK is enabled for shifting data on SDI into the
mode control registers. In the parallel programming mode
(PAR/SER = VDD),CScontrolstheclockdutycyclestabilizer
(See Table 2). CS can be driven with 1.8V to 3.3V logic.
SCK (Pin 21): In Serial Programming Mode, (PAR/SER =
0V), SCK Is the Serial Interface Clock Input. In the parallel
programming mode (PAR/SER = VDD), SCK controls the
digital output mode (see Table 2). SCK can be driven with
1.8V to 3.3V logic.
SDI (Pin 22): In Serial Programming Mode, (PAR/SER =
0V), SDI Is the Serial Interface Data Input. Data on SDI
is clocked into the mode control registers on the rising
edge of SCK. In the parallel programming mode (PAR/
SER = VDD), SDI can be used together with SDO to power
down the part (see Table 2). SDI can be driven with 1.8V
to 3.3V logic.
OGND (Pin 41): Output Driver Ground. Must be shorted
to the ground plane by a very low inductance path. Use
multiple vias close to the pin.
OVDD (Pin 42): Output Driver Supply. Bypass to ground
with a 0.1μF ceramic capacitor.
SDO (Pin 61): In Serial Programming Mode, (PAR/SER
= 0V), SDO Is the Optional Serial Interface Data Output.
Data on SDO is read back from the mode control regis-
ters and can be latched on the falling edge of SCK. SDO
is an open-drain NMOS output that requires an external
2k pull-up resistor to 1.8V – 3.3V. If read back from the
mode control registers is not needed, the pull-up resistor
is not necessary and SDO can be left unconnected. In the
parallel programming mode (PAR/SER = VDD), SDO can
be used together with SDI to power down the part (see
Table 2). When used as an input, SDO can be driven with
1.8V to 3.3V logic through a 1k series resistor.
VREF (Pin 62): Reference Voltage Output. Bypass to
ground with a 2.2μF ceramic capacitor. The output voltage
is nominally 1.25V.
PIN FUNCTIONS
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| LTC2150-14 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:300MHz Digital Predistortion Receiver |
| LTC2150CUJ-12#PBF | 制造商:Linear Technology 功能描述:IC ADC 12BIT 170MSPS 40QFN 制造商:Linear Technology 功能描述:ADC 12BIT 170MSPS SPI QFN-40 制造商:Linear Technology 功能描述:ADC, 12BIT, 170MSPS, SPI, QFN-40 制造商:Linear Technology 功能描述:ADC, 12BIT, 170MSPS, SPI, QFN-40, Resolution (Bits):12bit, Sampling Rate:170MSPS, Supply Voltage Type:Single, Supply Voltage Min:1.7V, Supply Voltage Max:1.9V, Supply Current:145mA, Digital IC Case Style:QFN, No. of Pins:40 , RoHS Compliant: Yes 制造商:Linear Technology 功能描述:MS-ADC/High Speed, 12-bit, 170Msps, 1.8V ADC, DDR LVDS Outputs |
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| LTC2150CUJ-14#PBF | 制造商:Linear Technology 功能描述:IC ADC DUAL 14BIT 170MSPS 40-QFN |
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