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參數(shù)資料
| 型號(hào)： | LTC2156CUP-14#PBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | 2-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64 |
| 封裝： | 9 X 9 MM, LEAD FREE, PLASTIC, MO-220WNJR-5, QFN-64 |
| 文件頁數(shù)： | 1/32頁 |
| 文件大小： | 647K |
| 代理商： | LTC2156CUP-14#PBF |
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1
21576514f
LTC2157-14/
LTC2156-14/LTC2155-14
TYPICAL APPLICATION
FEATURES
APPLICATIONS
DESCRIPTION
Dual 14-Bit 250Msps/
210Msps/170Msps ADCs
n Communications
n Cellular Basestations
n Software Defined Radios
n Medical Imaging
n High Definition Video
n Testing and Measurement Instruments
n 70dB SNR
n 90dB SFDR
n Low Power: 650mW/616mW/567mW Total
n Single 1.8V Supply
n DDR LVDS Outputs
n Easy-to-Drive 1.5VP-P Input Range
n 1.25GHz Full Power Bandwidth S/H
n Optional Clock Duty Cycle Stabilizer
n Low Power Sleep and Nap Modes
n Serial SPI Port for Configuration
n Pin-Compatible 12-Bit Versions
n 64-Pin (9mm × 9mm) QFN Package
The LTC
2157-14/LTC2156-14/LTC2155-14 are 2-channel
simultaneous sampling 250Msps/210Msps/170Msps
14-bit A/D converters designed for digitizing high fre-
quency, wide dynamic range signals. They are perfect
for demanding communications applications with AC
performance that includes 70dB SNR and 90dB spurious
free dynamic range (SFDR). The 1.25GHz input bandwidth
allows the ADC to undersample high frequencies with
good performance. The latency is only five clock cycles.
DC specs include ±0.85LSB INL (typ), ±0.25LSB DNL (typ)
and no missing codes over temperature. The transition
noise is 1.82LSBRMS.
The digital outputs are double data rate (DDR) LVDS.
The ENC+ and ENC– inputs can be driven differentially with
a sine wave, PECL, LVDS, TTL, or CMOS inputs. An optional
clock duty cycle stabilizer allows high performance at full
speed for a wide range of clock duty cycles.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
S/H
CORRECTION
LOGIC
OUTPUT
DRIVERS
14-BIT
PIPELINED
ADC CORE
CLOCK/DUTY
CYCLE
CONTROL
DA12_13
DA0_1
DB12_13
DB0_1
CLOCK
ANALOG
INPUT
21576514 TA01
DDR
LVDS
DDR
LVDS
VDD
OVDD
OGND
GND
CHANNEL A
S/H
CORRECTION
LOGIC
OUTPUT
DRIVERS
14-BIT
PIPELINED
ADC CORE
ANALOG
INPUT
OGND
OVDD
CHANNEL B
FREQUENCY (MHz)
0
–120
AMPLITUDE
(dBFS)
–100
–80
–60
–40
0
20
40
60
80
21576514 TA01b
100
120
–20
LTC2157-14 32K Point FFT,
fIN = 15MHz, –1dBFS, 250Msps
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LTC2157IUP-14#TRPBF | 2-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64 |
| LTC2155IUP-14#PBF | 2-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64 |
| LTC2160CUK#TRPBF | 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48 |
| LTC2160IUK#PBF | 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48 |
| LTC2160IUK#TRPBF | 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LTC2156IUP-12 | 制造商:Linear Technology 功能描述:ADC DUAL 12BIT 210M 64QFN 制造商:Linear Technology 功能描述:ADC, DUAL, 12BIT, 210M, 64QFN |
| LTC2156IUP-12#PBF | 功能描述:IC ADC DUAL 12BIT 210M 64-QFN RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個(gè)單端，單極；2 個(gè)差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| LTC2156IUP-12#TRPBF | 制造商:Linear Technology 功能描述:IC ADC DUAL 12BIT 210M 64-QFN |
| LTC2156IUP-14#PBF | 制造商:Linear Technology 功能描述:IC ADC DUAL 210MSPS 64-QFN |
| LTC2156IUP-14#TRPBF | 制造商:Linear Technology 功能描述:IC ADC DUAL 210MSPS 64-QFN |
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