參數(shù)資料
型號(hào): LTC2202IUK#TRPBF
廠商: Linear Technology
文件頁(yè)數(shù): 19/32頁(yè)
文件大?。?/td> 0K
描述: IC ADC 16-BIT 10MSPS 48-QFN
標(biāo)準(zhǔn)包裝: 2,000
位數(shù): 16
采樣率(每秒): 10M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 165mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-WFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 48-QFN-EP(7x7)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 1 個(gè)差分
配用: DC919A-F-ND - BOARD DEMO 16BIT MSPS LTC2202
DC890B-ND - BOARD USB DATA COLLECTION
LTC2203/LTC2202
26
22032fd
Figure 12. Functional Equivalent Block Diagram of
Internal Dither Circuit
S/H
AMP
DIGITAL
SUMMATION
OUTPUT
DRIVERS
MULTIBIT DEEP
PSEUDO-RANDOM
NUMBER
GENERATOR
16-BIT
PIPELINED
ADC CORE
PRECISION
DAC
CLOCK/DUTY
CYCLE
CONTROL
CLKOUT+
CLKOUT
OF
D15
D0
CLK
DITHER ENABLE
HIGH = DITHER ON
LOW = DITHER OFF
DITH
ANALOG
AIN
+
AIN
INPUT
22032 F13
LTC2203/LTC2202
Internal Dither
The LTC2203/LTC2202 are 16-bit ADCs with very linear
transfer functions; however, at low input levels even
slight imperfections in the transfer function will result in
unwanted tones. Small errors in the transfer function are
usually a result of ADC element mismatches. An optional
internal dither mode can be enabled to randomize the
input’s location on the ADC transfer curve, resulting in
improved SFDR for low signal levels.
As shown in Figure 12, the output of the sample-and-hold
amplier is summed with the output of a dither DAC. The
dither DAC is driven by a long sequence pseudo-random
number generator; the random number fed to the dither
DAC is also subtracted from the ADC result. If the dither
DAC is precisely calibrated to the ADC, very little of the
dither signal will be seen at the output. The dither signal
that does leak through will appear as white noise. The dither
DAC is calibrated to result in less than 0.5dB elevation in
the noise oor of the ADC, as compared to the noise oor
with dither off.
Grounding and Bypassing
The LTC2203/LTC2202 require a printed circuit board with a
clean unbroken ground plane; a multilayer board with an
internal ground plane is recommended. The pinout of the
LTC2203/LTC2202 has been optimized for a owthrough
layout so that the interaction between inputs and digital
outputs is minimized. Layout for the printed circuit board
should ensure that digital and analog signal lines are
separated as much as possible. In particular, care should
be taken not to run any digital track alongside an analog
signal track or underneath the ADC.
High quality ceramic bypass capacitors should be used
at the VDD, VCM, and OVDD pins. Bypass capacitors must
be located as close to the pins as possible. The traces
connecting the pins and bypass capacitors must be kept
short and should be made as wide as possible.
The LTC2203/LTC2202 differential inputs should run
parallel and close to each other. The input traces should
be as short as possible to minimize capacitance and to
minimize noise pickup.
Heat Transfer
Most of the heat generated by the LTC2203/LTC2202 is
transferred from the die through the bottom-side exposed
pad. For good electrical and thermal performance, the
exposed pad must be soldered to a large grounded pad
on the PC board. It is critical that the exposed pad and all
ground pins are connected to a ground plane of sufcient
area with as many vias as possible.
APPLICATIONS INFORMATION
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