參數(shù)資料
型號(hào)： LTC2207UK
廠商： Linear Technology Corporation
英文描述： 16-Bit, 105Msps/80Msps ADCs
中文描述： 16位，105Msps/80Msps模數(shù)轉(zhuǎn)換器
文件頁(yè)數(shù)： 17/32頁(yè)
文件大?。?/td> 1489K
代理商： LTC2207UK
LTC2207/LTC2206
17
22076fa
CONVERTER OPERATION
The LTC2207/LTC2206 are CMOS pipelined multistep con-
verters with a front-end PGA. As shown in Figure 1, the con-
verter has five pipelined ADC stages; a sampled analog input
will result in a digitized value seven cycles clock later (see the
Timing Diagram section). The analog input is differential for
improved common mode noise immunity and to maximize
the input range. Additionally, the differential input drive
will reduce even order harmonics of the sample and hold
circuit. The encode input is also differential for improved
common mode noise immunity.
The LTC2207/LTC2206 have two phases of operation,
determined by the state of the differential ENC
+
/ENC
–
input pins. For brevity, the text will refer to ENC
+
great-
er than ENC
–
as ENC high and ENC
+
less than ENC
–
as
ENC low.
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage amplifier. In
operation, the ADC quantizes the input to the stage and
the quantized value is subtracted from the input by the
DAC to produce a residue. The residue is amplified and
output by the residue amplifier. Successive stages oper-
ate out of phase so that when odd stages are outputting
their residue, the even stages are acquiring that residue
and vice versa.
When ENC is low, the analog input is sampled differen-
tially directly onto the input sample-and-hold capacitors,
inside the “input S/H” shown in the block diagram. At the
instant that ENC transitions from low to high, the voltage
on the sample capacitors is held. While ENC is high, the
held input voltage is buffered by the S/H amplifier which
drives the first pipelined ADC stage. The first stage acquires
the output of the S/H amplifier during the high phase of
ENC. When ENC goes back low, the first stage produces
its residue which is acquired by the second stage. At the
same time, the input S/H goes back to acquiring the analog
input. When ENC goes high, the second stage produces
its residue which is acquired by the third stage. An iden-
tical process is repeated for the third and fourth stages,
resulting in a fourth stage residue that is sent to the fifth
stage for final evaluation.
Each ADC stage following the first has additional range to
accommodate flash and amplifier offset errors. Results
from all of the ADC stages are digitally delayed such that
the results can be properly combined in the correction
logic before being sent to the output buffer.
APPLICATIONS INFORMATION
相關(guān)PDF資料
PDF描述
LTC2208-14 14-Bit, 130Msps ADC
LTC2208CUP-14 14-Bit, 130Msps ADC
LTC2208IUP-14 14-Bit, 130Msps ADC
LTC2208UP-14 14-Bit, 130Msps ADC
LTC2208 16-Bit, 130Msps ADC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LTC2207UK-14 制造商:LINER 制造商全稱:Linear Technology 功能描述:14-Bit, 105Msps/80Msps ADCs
LTC2208 制造商:LINER 制造商全稱:Linear Technology 功能描述:Dual 14-Bit 250Msps
LTC2208-14 制造商:LINER 制造商全稱:Linear Technology 功能描述:14-Bit, 130Msps ADC
LTC2208CUP 制造商:Linear Technology 功能描述:IC ADC 16BIT 130MSPS 64-QFN
LTC2208CUP#PBF 制造商:Linear Technology 功能描述:Single ADC Pipelined 130Msps 16-bit Parallel/LVDS 64-Pin QFN EP Cut Tape 制造商:Linear Technology 功能描述:IC ADC 16BIT 130MSPS 64-QFN 制造商:Linear Technology 功能描述:ADC 16BIT 3.3VIN 130MSPS 64QFN 制造商:Linear Technology 功能描述:ADC, 16BIT, 3.3VIN, 130MSPS, 64QFN 制造商:Linear Technology 功能描述:MS-ADC/High Speed, 16-bit, 130Msps ADC 制造商:Linear Technology 功能描述:IC, ADC, 16BIT, 130MSPS, QFN-64, Resolution (Bits):16bit, Sampling Rate:130MSPS, Supply Voltage Type:Single, Supply Voltage Min:3.135V, Supply Voltage Max:3.465V, Supply Current:380mA, Digital IC Case Style:QFN, No. of Pins:64 , RoHS Compliant: Yes
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