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參數(shù)資料
| 型號： | LTC2208CUP-14#PBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | 16-Bit, 130Msps ADC; Package: QFN; No of Pins: 64; Temperature Range: 0°C to +70°C |
| 中文描述： | 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64 |
| 封裝： | 9 X 9 MM, LEAD FREE, PLASTIC, MO-220WNJR-5, QFN-64 |
| 文件頁數(shù)： | 1/28頁 |
| 文件大?。?/td> | 708K |
| 代理商： | LTC2208CUP-14#PBF |
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LTC2208-14
1
220814fb
14-Bit, 130Msps ADC
The LTC2208-14 is a 130Msps, sampling 14-bit A/D
converter designed for digitizing high frequency, wide
dynamic range signals with input frequencies up to
700MHz. The input range of the ADC can be optimized
with the PGA front end.
The LTC2208-14 is perfect for demanding communications
applications, with AC performance that includes 77.1dBFS
Noise Floor and 98dB spurious free dynamic range (SFDR).
Ultralow jitter of 70fsRMS allows undersampling of high
input frequencies with excellent noise performance.
Maximum DC specs include ±1.5LSB INL, ±0.5LSB DNL
(no missing codes).
The digital output can be either differential LVDS or
single-ended CMOS. There are two format options for the
CMOS outputs: a single bus running at the full data rate or
demultiplexed buses running at half data rate. A separate
output power supply allows the CMOS output swing to
range from 0.5V to 3.6V.
The ENC+ and ENC– inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL or
CMOS inputs. An optional clock duty cycle stabilizer al-
lows high performance at full speed with a wide range of
clock duty cycles.
n Telecommunications
n Receivers
n Cellular Base Stations
n Spectrum Analysis
n Imaging Systems
n ATE
n Sample Rate: 130Msps
n 77.1dBFS Noise Floor
n 98dB SFDR
n SFDR >81dB at 250MHz (1.5VP-P Input Range)
n PGA Front End (2.25VP-P or 1.5VP-P Input Range)
n 700MHz Full Power Bandwidth S/H
n Optional Internal Dither
n Optional Data Output Randomizer
n LVDS or CMOS Outputs
n Single 3.3V Supply
n Power Dissipation: 1.32W
n Clock Duty Cycle Stabilizer
n Pin Compatible 16-Bit Version
130Msps: LTC2208 (16-Bit)
n 64-Pin (9mm
× 9mm) QFN Package
32k Point FFT, fIN = 15.11MHz,
–1dB, PGA = 0, RAND “On”,
Dither “OFF”
–
+
S/H
AMP
CORRECTION
LOGIC AND
SHIFT REGISTER
OUTPUT
DRIVERS
14-BIT
PIPELINED
ADC CORE
INTERNAL ADC
REFERENCE
GENERATOR
1.25V
COMMON MODE
BIAS VOLTAGE
CLOCK/DUTY
CYCLE
CONTROL
D13
D0
PGA
SHDN
DITH
MODE
LVDS
RAND
VCM
ANALOG
INPUT
220814 TA01
CMOS
OR
LVDS
0.5V TO 3.6V
3.3V
SENSE
OGND
OVDD
2.2μF
0.1μF
VDD
GND
ADC CONTROL INPUTS
AIN+
ENC +
AIN–
ENC –
OF
CLKOUT
FREQUENCY (MHz)
0
AMPLITUDE
(dBFS)
–80
–20
–10
0
20
40
50
220814 G05
–100
–110
–40
–60
–90
–30
–120
–50
–70
10
30
60
TYPICAL APPLICATION
DESCRIPTION
FEATURES
APPLICATIONS
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
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