denotes the specifications which apply over the ful" />
參數(shù)資料
型號(hào): LTC2220IUP#TRPBF
廠商: Linear Technology
文件頁數(shù): 28/32頁
文件大小: 0K
描述: IC ADC 12BIT 170MSPS 64-QFN
標(biāo)準(zhǔn)包裝: 2,000
位數(shù): 12
采樣率(每秒): 170M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 1.18W
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 64-QFN(9x9)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 1 個(gè)單端,雙極; 1 個(gè)差分,雙極
LTC2220/LTC2221
5
22201fa
TI I G CHARACTERISTICS
U
W
The
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
POWER REQUIRE E TS
W
U
The
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 9)
LTC2220
LTC2221
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
VDD
Analog Supply Voltage
(Note 8)
3.1
3.3
3.5
3.1
3.3
3.5
V
PSHDN
Shutdown Power
SHDN = High, OE = High, No CLK
2
mW
PNAP
Nap Mode Power
SHDN = High, OE = Low, No CLK
35
mW
LVDS OUTPUT MODE
OVDD
Output Supply Voltage
(Note 8)
3
3.3
3.6
3
3.3
3.6
V
IVDD
Analog Supply Current
264
288
196
212
mA
IOVDD
Output Supply Current
55
70
55
70
mA
PDISS
Power Dissipation
1050
1182
828
931
mW
CMOS OUTPUT MODE
OVDD
Output Supply Voltage
(Note 8)
0.5
3.3
3.6
0.5
3.3
3.6
V
IVDD
Analog Supply Current
264
288
196
212
mA
PDISS
Power Dissipation
890
660
mW
LTC2220
LTC2221
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
fS
Sampling Frequency
(Note 8)
1
170
1
135
MHz
tL
ENC Low Time (Note 7)
Duty Cycle Stabilizer Off
2.8
2.94
500
3.5
3.7
500
ns
Duty Cycle Stabilizer On
2
2.94
500
2
3.7
500
ns
tH
ENC High Time (Note 7)
Duty Cycle Stabilizer Off
2.8
2.94
500
3.5
3.7
500
ns
Duty Cycle Stabilizer On
2
2.94
500
2
3.7
500
ns
tAP
Sample-and-Hold Aperture Delay
0
ns
tOE
Output Enable Delay
(Note 7)
510
ns
LVDS OUTPUT MODE
tD
ENC to DATA Delay
(Note 7)
1.3
2.2
3.5
1.3
2.2
3.5
ns
tC
ENC to CLOCKOUT Delay
(Note 7)
1.3
2.2
3.5
1.3
2.2
3.5
ns
DATA to CLOCKOUT Skew
(tC - tD) (Note 7)
–0.6
0
0.6
–0.6
0
0.6
ns
Rise Time
0.5
ns
Fall Time
0.5
ns
Pipeline Latency
5
Cycles
CMOS OUTPUT MODE
tD
ENC to DATA Delay
(Note 7)
1.3
2.1
3.5
1.3
2.1
3.5
ns
tC
ENC to CLOCKOUT Delay
(Note 7)
1.3
2.1
3.5
1.3
2.1
3.5
ns
DATA to CLOCKOUT Skew
(tC - tD) (Note 7)
–0.6
0
0.6
–0.6
0
0.6
ns
Pipeline Latency Full Rate CMOS
5
Cycles
Demuxed Interleaved
5
Cycles
Demuxed Simultaneous
5 and 6
Cycles
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