POWER REQUIREMENTS The l deno" />
參數(shù)資料
型號(hào)： LTC2226IUH#TRPBF
廠商： Linear Technology
文件頁(yè)數(shù)： 24/28頁(yè)
文件大小： 0K
描述： IC ADC 12BIT 25MSPS SAMPL 32-QFN
標(biāo)準(zhǔn)包裝： 2,500
位數(shù)： 12
采樣率（每秒）： 25M
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 90mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-WFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 32-QFN 裸露焊盤(pán)（5x5）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 1 個(gè)單端，雙極; 1 個(gè)差分，雙極
LTC2228/LTC2227/LTC2226
5
222876fb
POWER REQUIREMENTS The l denotes the specications which apply over the full operating temperature
range, otherwise specications are at TA = 25°C. (Note 8)
SYMBOL
PARAMETER
CONDITIONS
LTC2228
LTC2227
LTC2226
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
VDD
Analog Supply Voltage (Note 9)
l
2.7
3
3.4
2.7
3
3.4
2.7
3
3.4
V
OVDD
Output Supply Voltage (Note 9)
l
0.5
3
3.6
0.5
3
3.6
0.5
3
3.6
V
IVDD
Supply Current
l
68.3
80
40
48
25
30
mA
PDISS
Power Dissipation
l
205
240
120
144
75
90
mW
PSHDN
Shutdown Power
SHDN = H, OE = H,
No CLK
222
mW
PNAP
Nap Mode Power
SHDN = H, OE = L,
No CLK
15
mW
TIMING CHARACTERISTICS The l denotes the specications which apply over the full operating temperature
range, otherwise specications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
LTC2228
LTC2227
LTC2226
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
fS
Sampling Frequency
(Note 9)
l
1
65
1
40
1
25
MHz
tL
CLK Low Time
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
(Note 7)
l
7.3
5
7.7
500
11.8
5
12.5
500
18.9
5
20
500
ns
tH
CLK High Time
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
(Note 7)
l
7.3
5
7.7
500
11.8
5
12.5
500
18.9
5
20
500
ns
tAP
Sample-and-Hold
Aperture Delay
000
ns
tD
CLK to DATA Delay
CL = 5pF (Note 7)
l
1.4
2.7
5.4
1.4
2.7
5.4
1.4
2.7
5.4
ns
Data Access Time
After OE
↓
CL = 5pF (Note 7)
l
4.3
10
4.3
10
4.3
10
ns
BUS Relinquish Time
(Note 7)
l
3.3
8.5
3.3
8.5
3.3
8.5
ns
Pipeline
Latency
5
Cycles
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground with GND and OGND
wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: VDD = 3V, fSAMPLE = 65MHz (LTC2228), 40MHz (LTC2227), or
25MHz (LTC2226), input range = 2VP-P with differential drive, unless
otherwise noted.
Note 5: Integral nonlinearity is dened as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 6: Offset error is the offset voltage measured from –0.5 LSB when
the output code ickers between 0000 0000 0000 and 1111 1111 1111.
Note 7: Guaranteed by design, not subject to test.
Note 8: VDD = 3V, fSAMPLE = 65MHz (LTC2228), 40MHz (LTC2227), or
25MHz (LTC2226), input range = 1VP-P with differential drive.
Note 9: Recommend operating conditions.
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