參數(shù)資料
型號(hào)： LTC2227CUH#TRPBF
廠商： Linear Technology
文件頁(yè)數(shù)： 14/28頁(yè)
文件大?。?/td> 0K
描述： IC ADC 12BIT 40MSPS SAMPL 32-QFN
標(biāo)準(zhǔn)包裝： 2,500
位數(shù)： 12
采樣率（每秒）： 40M
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 144mW
電壓電源： 單電源
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 32-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 32-QFN 裸露焊盤（5x5）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 1 個(gè)單端，雙極; 1 個(gè)差分，雙極
LTC2228/LTC2227/LTC2226
21
222876fb
APPLICATIONS INFORMATION
Maximum and Minimum Conversion Rates
The maximum conversion rate for the LTC2228/LTC2227/
LTC2226 is 65Msps (LTC2228), 40Msps (LTC2227), and
25Msps (LTC2226). For the ADC to operate properly, the
CLK signal should have a 50% (±5%) duty cycle. Each
half cycle must have at least 7.3ns (LTC2228), 11.8ns
(LTC2227), and 18.9ns (LTC2226) for the ADC internal cir-
cuitry to have enough settling time for proper operation.
An optional clock duty cycle stabilizer circuit can be used
if the input clock has a non 50% duty cycle. This circuit
uses the rising edge of the CLK pin to sample the analog
input. The falling edge of CLK is ignored and the internal
falling edge is generated by a phase-locked loop. The input
clock duty cycle can vary from 40% to 60% and the clock
duty cycle stabilizer will maintain a constant 50% internal
duty cycle. If the clock is turned off for a long period of
time, the duty cycle stabilizer circuit will require a hundred
clock cycles for the PLL to lock onto the input clock. To
use the clock duty cycle stabilizer, the MODE pin should be
connected to 1/3VDD or 2/3VDD using external resistors.
The lower limit of the LTC2228/LTC2227/LTC2226 sample
rate is determined by droop of the sample-and-hold circuits.
The pipelined architecture of this ADC relies on storing
analog signals on small-valued capacitors. Junction leak-
age will discharge the capacitors. The specied minimum
operating frequency for the LTC2228/LTC2227/LTC2226
is 1Msps.
LTC2228/27/26
222876 F14
OVDD
VDD
0.1μF
43Ω
TYPICAL
DATA
OUTPUT
OGND
OVDD
0.5V
TO 3.6V
PREDRIVER
LOGIC
DATA
FROM
LATCH
OE
Figure 14. Digital Output Buffer
DIGITAL OUTPUTS
Table 1 shows the relationship between the analog input
voltage, the digital data bits and the overow bit.
Table 1. Output Codes vs Input Voltage
AIN+ – AIN–
(2V RANGE)
OF
D11-D0
(OFFSET BINARY)
D11-D0
(2’s COMPLEMENT)
>+1.000000V
+0.999512V
+0.999024V
1
0
1111 1111 1111
1111 1111 1110
0111 1111 1111
0111 1111 1110
+0.000488V
0.000000V
–0.000488V
–0.000976V
0
1000 0000 0001
1000 0000 0000
0111 1111 1111
0111 1111 1110
0000 0000 0001
0000 0000 0000
1111 1111 1111
1111 1111 1110
–0.999512V
–1.000000V
<–1.000000V
0
1
0000 0000 0001
0000 0000 0000
1000 0000 0001
1000 0000 0000
Digital Output Buffers
Figure 14 shows an equivalent circuit for a single output
buffer. Each buffer is powered by OVDD and OGND, isolated
from the ADC power and ground. The additional
N-channel transistor in the output driver allows operation
down to low voltages. The internal resistor in series with
the output makes the output appear as 50Ω to external
circuitry and may eliminate the need for external damping
resistors.
As with all high speed/high resolution converters, the
digital output loading can affect the performance. The
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