參數(shù)資料
型號(hào): LTC2234IUK
廠商: Linear Technology
文件頁(yè)數(shù): 10/24頁(yè)
文件大?。?/td> 0K
描述: IC ADC 10BIT 135MSPS SAMPL 48QFN
標(biāo)準(zhǔn)包裝: 52
位數(shù): 10
采樣率(每秒): 135M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 680mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 48-WFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 48-QFN-EP(7x7)
包裝: 管件
輸入數(shù)目和類(lèi)型: 1 個(gè)單端,雙極; 1 個(gè)差分,雙極
LTC2234
18
2234fa
DIGITAL OUTPUTS
Table 1 shows the relationship between the analog input
voltage, the digital data bits and the overflow bit.
APPLICATIO S I FOR ATIO
WU
UU
LTC2234
2234 F13
OVDD
VDD
0.1
F
43
TYPICAL
DATA
OUTPUT
OGND
OVDD
0.5V
TO 3.6V
PREDRIVER
LOGIC
DATA
FROM
LATCH
OE
Figure 13. Digital Output Buffer
Digital Output Buffers
Figure 13 shows an equivalent circuit for a single output
buffer. Each buffer is powered by OVDD and OGND, which
are isolated from the ADC power and ground. The addi-
tional N-channel transistor in the output driver allows
operation down to voltages as low as 0.5V. The internal
resistor in series with the output makes the output appear
as 50
to external circuitry and may eliminate the need for
external damping resistors.
2234 F12a
ENC
1.6V
VTHRESHOLD = 1.6V
ENC+
0.1
F
LTC2234
2234 F12b
ENC
ENC+
130
3.3V
130
D0
Q0
MC100LVELT22
LTC2234
83
83
Figure 12a. Single-Ended ENC Drive,
Not Recommended for Low Jitter
Figure 12b. ENC Drive Using a CMOS to PECL Translator
Table 2. MODE Pin Function
Clock Duty
MODE Pin
Output Format
Cycle Stablizer
0
Offset Binary
Off
1/3VDD
Offset Binary
On
2/3VDD
2’s Complement
On
VDD
2’s Complement
Off
As with all high speed/high resolution converters, the
digital output loading can affect the performance. The
digital outputs of the LTC2234 should drive a minimal
capacitive load to avoid possible interaction between the
digital outputs and sensitive input circuitry. For full speed
operation the capacitive load should be kept under 5pF.
Lower OVDD voltages will also help reduce interference
from the digital outputs and improve the SNR.
Data Format
The LTC2234 parallel digital output can be selected for
offset binary or 2’s complement format. The format is
selected with the MODE pin. Connecting MODE to GND or
1/3VDD selects offset binary output format. Connecting
MODE to 2/3VDD or VDD selects 2’s complement output
format. An external resistor divider can be used to set the
1/3VDD or 2/3VDD logic values. Table 2 shows the logic
states for the MODE pin.
Table 1. Output Codes vs Input Voltage
AIN+ – AIN–
D9 – D0
(2V Range)
OF
(Offset Binary)
(2’s Complement)
>+1.000000V
1
11 1111 1111
01 1111 1111
+0.998047V
0
11 1111 1111
01 1111 1111
+0.996094V
0
11 1111 1110
01 1111 1110
+0.001953V
0
10 0000 0001
00 0000 0001
0.000000V
0
10 0000 0000
00 0000 0000
–0.001953V
0
01 1111 1111
11 1111 1111
–0.003906V
0
01 1111 1110
11 1111 1110
–0.998047V
0
00 0000 0001
10 0000 0001
–1.000000V
0
00 0000 0000
10 0000 0000
<–1.000000V
1
00 0000 0000
10 0000 0000
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LTC2234IUK#PBF 功能描述:IC ADC 10BIT 135MSPS SAMPL 48QFN RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率(每秒):20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散(最大):155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP(7x7) 包裝:Digi-Reel® 輸入數(shù)目和類(lèi)型:4 個(gè)單端,單極;2 個(gè)差分,單極 產(chǎn)品目錄頁(yè)面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6
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LTC2234IUK#TRPBF 功能描述:IC ADC 10BIT 135MSPS SAMPL 48QFN RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):12 采樣率(每秒):3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散(最大):- 電壓電源:- 工作溫度:- 安裝類(lèi)型:表面貼裝 封裝/外殼:SOT-23-6 供應(yīng)商設(shè)備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類(lèi)型:-
LTC2234UK 制造商:LINER 制造商全稱:Linear Technology 功能描述:10-Bit, 135Msps ADC
LTC2236 制造商:LINER 制造商全稱:Linear Technology 功能描述:14-Bit, 80Msps Low Power 3V ADC