AIN+
參數(shù)資料
型號(hào)： LTC2242IUP-10#PBF
廠商： Linear Technology
文件頁(yè)數(shù)： 13/30頁(yè)
文件大?。?/td> 0K
描述： IC ADC 10BIT 250MSPS 64-QFN
標(biāo)準(zhǔn)包裝： 40
位數(shù)： 10
采樣率（每秒）： 250M
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 975mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 64-WFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 64-QFN（9x9）
包裝： 管件
輸入數(shù)目和類(lèi)型： 1 個(gè)差分，雙極
LTC2242-10
20
224210fd
applicaTions inForMaTion
Table 1. Output Codes vs Input Voltage
AIN+ – AIN–
(2V Range)
OF
D9 – D0
(Offset Binary)
D9 – D0
(2’s Complement)
>+1.000000V
+0.998047V
+0.996094V
1
0
11 1111 1111
11 1111 1110
01 1111 1111
01 1111 1110
+0.001953V
0.000000V
–0.001953V
–0.003906V
0
10 0000 0001
10 0000 0000
01 1111 1111
01 1111 1110
00 0000 0001
00 0000 0000
11 1111 1111
11 1111 1110
–0.998047V
–1.000000V
<–1.000000V
0
1
00 0000 0001
00 0000 0000
10 0000 0001
10 0000 0000
Digital Output Modes
The LTC2242-10 can operate in several digital output
modes: LVDS, CMOS running at full speed, and CMOS
demultiplexed onto two buses, each of which runs at half
speed. In the demultiplexed CMOS modes the two buses
(referred to as bus A and bus B) can either be updated on
alternateclockcycles(interleavedmode)orsimultaneously
(simultaneousmode).Fordetailsontheclocktiming,refer
to the timing diagrams.
The LVDS pin selects which digital output mode the part
uses. This pin has a four-level logic input which should
be connected to GND, 1/3VDD, 2/3VDD or VDD. An external
resistor divider can be used to set the 1/3VDD or 2/3VDD
logicvalues.Table2showsthelogicstatesfortheLVDSpin.
Table 2. LVDS Pin Function
LVDS
DIGITAL OUTPUT MODE
GND
Full-Rate CMOS
1/3VDD
Demultiplexed CMOS, Simultaneous Update
2/3VDD
Demultiplexed CMOS, Interleaved Update
VDD
LVDS
Digital Output Buffers (CMOS Modes)
Figure 13a shows an equivalent circuit for a single
output buffer in the CMOS output mode. Each buffer is
powered by OVDD and OGND, which are isolated from the
ADCpowerandground.TheadditionalN-channeltransistor
in the output driver allows operation down to voltages as
low as 0.5V. The internal resistor in series with the output
makes the output appear as 50Ω to external circuitry and
may eliminate the need for external damping resistors.
As with all high speed/high resolution converters, the
digital output loading can affect the performance. The
digital outputs of the LTC2242-10 should drive a minimal
capacitive load to avoid possible interaction between the
digital outputs and sensitive input circuitry. The output
should be buffered with a device such as an 74VCX245
CMOS latch. For full speed operation the capacitive load
should be kept under 10pF.
Lower OVDD voltages will also help reduce interference
from the digital outputs.
Digital Output Buffers (LVDS Mode)
Figure 13b shows an equivalent circuit for a differential
output pair in the LVDS output mode. A 3.5mA current is
steered from OUT+ to OUT– or vice versa which creates a
±350mV differential voltage across the 100Ω termination
resistor at the LVDS receiver. A feedback loop regulates
the common mode output voltage to 1.25V. For proper
operation each LVDS output pair needs an external 100Ω
termination resistor, even if the signal is not used (such as
OF+/OF–orCLKOUT+/CLKOUT–).TominimizenoisethePC
board traces for each LVDS output pair should be routed
close together. To minimize clock skew all LVDS PC board
traces should have about the same length.
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