參數(shù)資料
型號(hào): LTC2245IUH#TRPBF
廠商: Linear Technology
文件頁數(shù): 6/20頁
文件大小: 0K
描述: IC ADC 14BIT 10MSPS 3V 32-QFN
標(biāo)準(zhǔn)包裝: 2,500
位數(shù): 14
采樣率(每秒): 10M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 69mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 32-QFN 裸露焊盤(5x5)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 1 個(gè)單端,雙極; 1 個(gè)差分,雙極
LTC2245
14
2245fa
DIGITAL OUTPUTS
Table 1 shows the relationship between the analog input
voltage, the digital data bits, and the overflow bit.
As with all high speed/high resolution converters, the
digital output loading can affect the performance. The
digital outputs of the LTC2245 should drive a minimal
capacitive load to avoid possible interaction between the
digital outputs and sensitive input circuitry. The output
should be buffered with a device such as an ALVCH16373
CMOS latch. For full speed operation the capacitive load
should be kept under 10pF.
Lower OVDD voltages will also help reduce interference
from the digital outputs.
Data Format
Using the MODE pin, the LTC2245 parallel digital output
can be selected for offset binary or 2’s complement
format. Connecting MODE to GND or 1/3VDD selects offset
binary output format. Connecting MODE to
2/3VDD or VDD selects 2’s complement output format.
An external resistor divider can be used to set the 1/3VDD
or 2/3VDD logic values. Table 2 shows the logic states for
the MODE pin.
APPLICATIO S I FOR ATIO
WU
UU
Digital Output Buffers
Figure 9 shows an equivalent circuit for a single output
buffer. Each buffer is powered by OVDD and OGND, iso-
lated from the ADC power and ground. The additional
N-channel transistor in the output driver allows operation
down to low voltages. The internal resistor in series with
the output makes the output appear as 50
to external
circuitry and may eliminate the need for external damping
resistors.
Table 1. Output Codes vs Input Voltage
AIN+ – AIN–
D13 – D0
(2V Range)
OF
(Offset Binary)
(2’s Complement)
>+1.000000V
1
11 1111 1111 1111
01 1111 1111 1111
+0.999878V
0
11 1111 1111 1111
01 1111 1111 1111
+0.999756V
0
11 1111 1111 1110
01 1111 1111 1110
+0.000122V
0
10 0000 0000 0001
00 0000 0000 0001
0.000000V
0
10 0000 0000 0000
00 0000 0000 0000
–0.000122V
0
01 1111 1111 1111
11 1111 1111 1111
–0.000244V
0
01 1111 1111 1110
11 1111 1111 1110
–0.999878V
0
00 0000 0000 0001
10 0000 0000 0001
–1.000000V
0
00 0000 0000 0000
10 0000 0000 0000
<–1.000000V
1
00 0000 0000 0000
10 0000 0000 0000
LTC2245
2245 F09
OVDD
VDD
0.1
F
43
TYPICAL
DATA
OUTPUT
OGND
OVDD
0.5V
TO 3.6V
PREDRIVER
LOGIC
DATA
FROM
LATCH
OE
Figure 9. Digital Output Buffer
Table 2. MODE Pin Function
Clock Duty
MODE Pin
Output Format
Cycle Stablizer
0
Offset Binary
Off
1/3VDD
Offset Binary
On
2/3VDD
2’s Complement
On
VDD
2’s Complement
Off
Overflow Bit
When OF outputs a logic high the converter is either
overranged or underranged.
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