參數(shù)資料
型號(hào)： LTC2264CUJ-12#PBF
廠商： Linear Technology
文件頁(yè)數(shù)： 19/34頁(yè)
文件大?。?/td> 0K
描述： IC ADC 12BIT SER/PAR 40M 40-QFN
標(biāo)準(zhǔn)包裝： 61
位數(shù)： 12
采樣率（每秒）： 40M
數(shù)據(jù)接口： Serial LVDS
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 169mW
電壓電源： 模擬和數(shù)字
工作溫度： 0°C ~ 70°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 40-WFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 40-QFN（6x6）
包裝： 管件
輸入數(shù)目和類(lèi)型： 2 Differential; 2 Single-Ended
配用： DC1371A-ND - BOARD USB DATA ACQUISITION HS
26
22654312fb
LTC2265-12/
LTC2264-12/LTC2263-12
APPLICATIONS INFORMATION
Serial Programming Mode
To use the serial programming mode, PAR/SER should be
tied to ground. The CS, SCK, SDI and SDO pins become
a serial interface that program the A/D mode control
registers. Data is written to a register with a 16-bit serial
word. Data can also be read back from a register to verify
its contents.
Serial data transfer starts when CS is taken low. The data
on the SDI pin is latched at the first 16 rising edges of
SCK. Any SCK rising edges after the first 16 are ignored.
The data transfer ends when CS is taken high again.
The first bit of the 16-bit input word is the R/W bit. The
next seven bits are the address of the register (A6:A0).
The final eight bits are the register data (D7:D0).
If the R/W bit is low, the serial data (D7:D0) will be written
to the register set by the address bits (A6:A0). If the R/W
bit is high, data in the register set by the address bits (A6:
Table 4. Serial Programming Mode Register Map (PAR/SER = GND)
REGISTER A0: RESET REGISTER (ADDRESS 00h)
D7
D6
D5
D4
D3
D2
D1
D0
RESET
X
Bit 7
RESET
Software Reset Bit
0 = Not Used
1 = Software Reset. All Mode Control Registers Are Reset to 00h. The ADC is momentarily placed in SLEEP mode.
This Bit Is Automatically Set Back to Zero at the End of the SPI Write Command.
The Reset Register is Write Only
Bits 6-0
Unused, Don’t Care Bits.
REGISTER A1: FORMAT AND POWER-DOWN REGISTER (ADDRESS 01h)
D7
D6
D5
D4
D3
D2
D1
D0
DCSOFF
RAND
TWOSCOMP
SLEEP
NAP_2
X
NAP_1
Bit 7
DCSOFF
Clock Duty Cycle Stabilizer Bit
0 = Clock Duty Cycle Stabilizer On
1 = Clock Duty Cycle Stabilizer Off. This is Not Recommended.
Bit 6
RAND
Data Output Randomizer Mode Control Bit
0 = Data Output Randomizer Mode Off
1 = Data Output Randomizer Mode On
Bit 5
TWOSCOMP
Two’s Complement Mode Control Bit
0 = Offset Binary Data Format
1 = Two’s Complement Data Format
Bits 4, 3, 0
SLEEP: NAP_2: NAP_1
Sleep/Nap Mode Control Bits
000 = Normal Operation
0X1 = Channel 1 in Nap Mode
01X = Channel 2 in Nap Mode
1XX = Sleep Mode. Both Channels are disabled
Note: Any Combination of Channels Can Be Placed in Nap Mode.
Bits 1, 2
Unused, Don’t Care Bit
A0) will be read back on the SDO pin (see the Timing Dia-
grams section). During a readback command the register
is not updated and data on SDI is ignored.
The SDO pin is an open-drain output that pulls to ground
witha200impedance.Ifregisterdataisreadbackthrough
SDO, an external 2k pull-up resistor is required. If serial
data is only written and readback is not needed, then SDO
can be left floating and no pull-up resistor is needed. Table
4 shows a map of the mode control registers.
Software Reset
If serial programming is used, the mode control registers
should be programmed as soon as possible after the power
supplies turn on and are stable. The first serial command
mustbeasoftwareresetwhichwillresetallregisterdatabits
to logic 0. To perform a software reset, bit D7 in the reset
register is written with a logic 1. After the reset SPI write
commandiscomplete,bitD7isautomaticallysetbacktozero.
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