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參數(shù)資料
| 型號： | LTC2280CUP#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 23/24頁 |
| 文件大小： | 0K |
| 描述： | IC ADC DUAL 10BIT 105MSPS 64-QFN |
| 標準包裝： | 40 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 105M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 630mW |
| 電壓電源： | 單電源 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 64-QFN（9x9） |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 2 個單端，雙極; 2 個差分, 雙極 |
| 產(chǎn)品目錄頁面： | 1349 (CN2011-ZH PDF) |
LTC2280
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PI FU CTIO S
AINA+ (Pin 1): Channel A Positive Differential Analog
Input.
AINA– (Pin 2): Channel A Negative Differential Analog
Input.
REFHA (Pins 3, 4): Channel A High Reference. Short
together and bypass to Pins 5, 6 with a 0.1
F ceramic chip
capacitor as close to the pin as possible. Also bypass to
Pins 5, 6 with an additional 2.2
F ceramic chip capacitor
and to ground with a 1
F ceramic chip capacitor.
REFLA (Pins 5, 6): Channel A Low Reference. Short
together and bypass to Pins 3, 4 with a 0.1
F ceramic chip
capacitor as close to the pin as possible. Also bypass to
Pins 3, 4 with an additional 2.2
F ceramic chip capacitor
and to ground with a 1
F ceramic chip capacitor.
VDD (Pins 7, 10, 18, 63): Analog 3V Supply. Bypass to
GND with 0.1
F ceramic chip capacitors.
CLKA (Pin 8): Channel A Clock Input. The input sample
starts on the positive edge.
CLKB (Pin 9): Channel B Clock Input. The input sample
starts on the positive edge.
REFLB (Pins 11, 12): Channel B Low Reference. Short
together and bypass to Pins 13, 14 with a 0.1
F ceramic
chip capacitor as close to the pin as possible. Also bypass
to Pins 13, 14 with an additional 2.2
F ceramic chip ca-
pacitor and to ground with a 1
F ceramic chip capacitor.
REFHB (Pins 13, 14): Channel B High Reference. Short
together and bypass to Pins 11, 12 with a 0.1
F ceramic
chip capacitor as close to the pin as possible. Also bypass
to Pins 11, 12 with an additional 2.2
F ceramic chip ca-
pacitor and to ground with a 1
F ceramic chip capacitor.
AINB– (Pin 15): Channel B Negative Differential Analog
Input.
AINB+ (Pin 16): Channel B Positive Differential Analog
Input.
GND (Pins 17, 64): ADC Power Ground.
SENSEB (Pin 19): Channel B Reference Programming Pin.
Connecting SENSEB to VCMB selects the internal reference
and a
±0.5V input range. VDD selects the internal reference
and a
±1V input range. An external reference greater than
0.5V and less than 1V applied to SENSEB selects an input
range of
±VSENSEB. ±1V is the largest valid input range.
VCMB (Pin 20): Channel B 1.5V Output and Input Common
Mode Bias. Bypass to ground with 2.2
F ceramic chip
capacitor. Do not connect to VCMA.
MUX (Pin 21): Digital Output Multiplexer Control. If MUX
is High, Channel A comes out on DA0-DA9, OFA; Channel B
comes out on DB0-DB9, OFB. If MUX is Low, the output
busses are swapped and Channel A comes out on DB0-
DB9, OFB; Channel B comes out on DA0-DA9, OFA. To
multiplex both channels onto a single output bus, connect
MUX, CLKA and CLKB together. (This is not recommended
at clock frequencies above 80Msps.)
SHDNB (Pin 22): Channel B Shutdown Mode Selection
Pin. Connecting SHDNB to GND and OEB to GND results
in normal operation with the outputs enabled. Connecting
SHDNB to GND and OEB to VDD results in normal opera-
tion with the outputs at high impedance. Connecting
SHDNB to VDD and OEB to GND results in nap mode with
the outputs at high impedance. Connecting SHDNB to VDD
and OEB to VDD results in sleep mode with the outputs at
high impedance.
OEB (Pin 23): Channel B Output Enable Pin. Refer to
SHDNB pin function.
NC (Pins 24 to 27, 41 to 44): Do Not Connect These Pins.
DB0 – DB9 (Pins 28 to 30, 33 to 39): Channel B Digital
Outputs. DB9 is the MSB.
OGND (Pins 31, 50): Output Driver Ground.
OVDD (Pins 32, 49): Positive Supply for the Output Driv-
ers. Bypass to ground with 0.1
F ceramic chip capacitor.
OFB (Pin 40): Channel B Overflow/Underflow Output.
High when an overflow or underflow has occurred.
DA0 – DA9 (Pins 45 to 48, 51 to 56): Channel A Digital
Outputs. DA9 is the MSB.
OFA (Pin 57): Channel A Overflow/Underflow Output.
High when an overflow or underflow has occurred.
OEA (Pin 58): Channel A Output Enable Pin. Refer to
SHDNA pin function.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LTC2280IUP | 制造商:LINER 制造商全稱:Linear Technology 功能描述:Dual 10-Bit, 105Msps Low Noise 3V ADC |
| LTC2280IUP#PBF | 功能描述:IC ADC DUAL 10BIT 105MSPS 64-QFN RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標準包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個單端，單極；2 個差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| LTC2280IUP#TRPBF | 功能描述:IC ADC DUAL 10BIT 105MSPS 64-QFN RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個單端，單極；1 個單端，雙極 |
| LTC2280UP | 制造商:LINER 制造商全稱:Linear Technology 功能描述:Dual 10-Bit, 105Msps Low Noise 3V ADC |
| LTC2281 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:Dual 10-Bit, 125Msps Low Power 3V ADC |
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