參數(shù)資料
| 型號： | LTC2281IUP#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 10/24頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 10BIT DUAL 64-QFN |
| 標準包裝： | 40 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 125M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉換器數(shù)目： | 2 |
| 功率耗散（最大）： | 915mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-WFQFN 裸露焊盤 |
| 供應商設備封裝： | 64-QFN（9x9） |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 2 個單端，雙極; 2 個差分, 雙極 |
LTC2281
18
2281fb
APPLICATIONS INFORMATION
Table 2. MODE Pin Function
MODE PIN
OUTPUT FORMAT
CLOCK DUTY
CYCLE STABILIZER
0
Offset Binary
Off
1/3VDD
Offset Binary
On
2/3VDD
2’s Complement
On
VDD
2’s Complement
Off
Overow Bit
When OF outputs a logic high the converter is either
overranged or underranged on channel A or channel B.
Note that both channels share a common OF pin, which
is not the case for slower pin compatible parts such as
the LTC2280 or LTC2289. OF is disabled when channel A
is in sleep or nap mode.
Output Clock
The ADC has a delayed version of the CLKB input available
as a digital output, CLKOUT. The falling edge of the CLKOUT
pin can be used to latch the digital output data. CLKOUT
is disabled when channel B is in sleep or nap mode.
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OVDD, should be tied
to the same power supply as for the logic being driven.
For example, if the converter is driving a DSP powered
by a 1.8V supply, then OVDD should be tied to that same
1.8V supply.
OVDD can be powered with any voltage from 500mV up to
3.6V. OGND can be powered with any voltage from GND
up to 1V and must be less than OVDD. The logic outputs
will swing between OGND and OVDD.
Output Enable
The outputs may be disabled with the output enable pin,
OE. OE high disables all data outputs including OF. The
data access and bus relinquish times are too slow to
allow the outputs to be enabled and disabled during full
speed operation. The output Hi-Z state is intended for use
during long periods of inactivity. Channels A and B have
independent output enable pins (OEA, OEB).
Sleep and Nap Modes
The converter may be placed in shutdown or nap modes to
conservepower.ConnectingSHDNtoGNDresultsinnormal
operation. Connecting SHDN to VDD and OE to VDD results
in sleep mode, which powers down all circuitry including
the reference and typically dissipates 1mW. When exiting
sleep mode it will take milliseconds for the output data
to become valid because the reference capacitors have to
recharge and stabilize. Connecting SHDN to VDD and OE
to GND results in nap mode, which typically dissipates
30mW. In nap mode, the on-chip reference circuit is kept
on, so that recovery from nap mode is faster than that
from sleep mode, typically taking 100 clock cycles. In both
sleep and nap modes, all digital outputs are disabled and
enter the Hi-Z state.
Channels A and B have independent SHDN pins (SHDNA,
SHDNB). Channel A is controlled by SHDNA and OEA,
and Channel B is controlled by SHDNB and OEB. The
nap, sleep and output enable modes of the two channels
are completely independent, so it is possible to have one
channel operating while the other channel is in nap or
sleep mode.
Digital Output Multiplexer
The digital outputs of the LTC2281 can be multiplexed onto
a single data bus if the sample rate is 80Msps or less. The
MUX pin is a digital input that swaps the two data bus-
ses. If MUX is High, Channel A comes out on DA0-DA9;
Channel B comes out on DB0-DB9. If MUX is Low, the
output busses are swapped and Channel A comes out on
DB0-DB9; Channel B comes out on DA0-DA9. To multiplex
both channels onto a single output bus, connect MUX,
CLKA and CLKB together (see the Timing Diagram for
the multiplexed mode). The multiplexed data is available
on either data bus—the unused data bus can be disabled
with its OE pin.
Grounding and Bypassing
The LTC2281 requires a printed circuit board with a clean,
unbroken ground plane. A multilayer board with an internal
ground plane is recommended. Layout for the printed
circuit board should ensure that digital and analog signal
lines are separated as much as possible. In particular, care
相關PDF資料 |
PDF描述 |
|---|---|
| LTC2282CUP#PBF | IC ADC DUAL 12BIT 105MSPS 64-QFN |
| LTC2284CUP#PBF | IC ADC DUAL 14BIT 105MSPS 64-QFN |
| LTC2285CUP#PBF | IC ADC DUAL 14BIT 125MSPS 64QFN |
| LTC2289IUP#PBF | IC ADC DUAL 10BIT 80MSPS 64QFN |
| LTC2290IUP#TRPBF | IC ADC DUAL 12BIT 10MSPS 64QFN |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| LTC2281IUP-TR | 制造商:LINER 制造商全稱:Linear Technology 功能描述:Dual 10-Bit, 125Msps Low Power 3V ADC |
| LTC2281IUP-TRPBF | 制造商:LINER 制造商全稱:Linear Technology 功能描述:Dual 10-Bit, 125Msps Low Power 3V ADC |
| LTC2281UP | 制造商:LINER 制造商全稱:Linear Technology 功能描述:Dual 10-Bit, 125Msps Low Power 3V ADC |
| LTC2282 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:Dual 12-Bit, 105Msps Low Power 3V ADC |
| LTC2282CUP | 制造商:Linear Technology 功能描述:ADC Dual Pipelined 105Msps 12-bit Parallel 64-Pin QFN EP |
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