參數(shù)資料
型號(hào)： LTC2282CUP#TRPBF
廠商： Linear Technology
文件頁(yè)數(shù)： 10/24頁(yè)
文件大小： 0K
描述： IC ADC DUAL 12BIT 105MSPS 64-QFN
標(biāo)準(zhǔn)包裝： 2,000
位數(shù)： 12
采樣率（每秒）： 105M
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 630mW
電壓電源： 單電源
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 64-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 64-QFN（9x9）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 2 個(gè)單端，雙極; 2 個(gè)差分, 雙極
LTC2282
18
2282fb
APPLICATIONS INFORMATION
Table 2. MODE Pin Function
MODE Pin
Output Format
Clock Duty
Cycle Stabilizer
0
Offset Binary
Off
1/3VDD
Offset Binary
On
2/3VDD
2’s Complement
On
VDD
2’s Complement
Off
Overow Bit
When OF outputs a logic high the converter is either over-
ranged or underranged.
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supplyforthedigitaloutputbuffers,OVDD,shouldbetiedtothe
samepowersupplyasforthelogicbeingdriven.Forexample,
if the converter is driving a DSP powered by a 1.8V supply,
then OVDD should be tied to that same 1.8V supply.
OVDD can be powered with any voltage from 500mV up to
3.6V. OGND can be powered with any voltage from GND
up to 1V and must be less than OVDD. The logic outputs
will swing between OGND and OVDD.
Output Enable
The outputs may be disabled with the output enable pin,
OE. OE high disables all data outputs including OF. The
data access and bus relinquish times are too slow to
allow the outputs to be enabled and disabled during full
speed operation. The output Hi-Z state is intended for use
during long periods of inactivity. Channels A and B have
independent output enable pins (OEA, OEB).
Sleep and Nap Modes
The converter may be placed in shutdown or nap modes
to conserve power. Connecting SHDN to GND results in
normal operation. Connecting SHDN to VDD and OE to VDD
results in sleep mode, which powers down all circuitry,
including the reference, and typically dissipates 1mW.
When exiting sleep mode, it will take milliseconds for the
output data to become valid because the reference capaci-
tors have to recharge and stabilize. Connecting SHDN to
VDD and OE to GND results in nap mode, which typically
dissipates 30mW. In nap mode, the on-chip reference circuit
is kept on, so that recovery from nap mode is faster than
that from sleep mode, typically taking 100 clock cycles. In
both sleep and nap modes, all digital outputs are disabled
and enter the Hi-Z state.
Channels A and B have independent SHDN pins (SHDNA,
SHDNB). Channel A is controlled by SHDNA and OEA, and
channel B is controlled by SHDNB and OEB. The nap, sleep
andoutputenablemodesofthetwochannelsarecompletely
independent, so it is possible to have one channel operating
while the other channel is in nap or sleep mode.
Digital Output Multiplexer
The digital outputs of the LTC2282 can be multiplexed onto
a single data bus if the sample rate is 80Msps, or less. The
MUX pin is a digital input that swaps the two data busses.
If MUX is high, channel A comes out on DA0-DA11, OFA;
channel B comes out on DB0-DB11, OFB. If MUX is low,
the output busses are swapped and channel A comes out
on DB0-DB11, OFB; channel B comes out on DA0-DA11,
OFA. To multiplex both channels onto a single output bus,
connect MUX, CLKA and CLKB together (see the Timing
Diagram for the multiplexed mode). The multiplexed data
is available on either data bus—the unused data bus can
be disabled with its OE pin.
Grounding and Bypassing
The LTC2282 requires a printed circuit board with a clean,
unbroken ground plane. A multilayer board with an internal
ground plane is recommended. Layout for the printed
circuit board should ensure that digital and analog signal
lines are separated as much as possible. In particular, care
should be taken not to run any digital track alongside an
analog signal track or underneath the ADC.
相關(guān)PDF資料
PDF描述
VE-BN1-IV-F4 CONVERTER MOD DC/DC 12V 150W
LTC2262CUJ-12#TRPBF IC ADC 12BIT 150MSPS 40-QFN
MS27473E18B11P CONN PLUG 11POS STRAIGHT W/PINS
AD7876CR-REEL IC ADC 12BIT SAMPLING 10V 24SOIC
AD976ABRZRL IC ADC 16BIT 200KSPS 28SOIC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LTC2282IUP 制造商:Linear Technology 功能描述:ADC Dual Pipelined 105Msps 12-bit Parallel 64-Pin QFN EP
LTC2282IUP#PBF 功能描述:IC ADC DUAL 12BIT 105MSPS 64-QFN RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:microPOWER™ 位數(shù):8 采樣率（每秒）:1M 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:- 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-VQFN 裸露焊盤（4x4） 包裝:Digi-Reel® 輸入數(shù)目和類型:8 個(gè)單端，單極 產(chǎn)品目錄頁(yè)面:892 (CN2011-ZH PDF) 其它名稱:296-25851-6
LTC2282IUP#TRPBF 功能描述:IC ADC DUAL 12BIT 105MSPS 64-QFN RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個(gè)單端，雙極
LTC2282IUP-PBF 制造商:LINER 制造商全稱:Linear Technology 功能描述:Dual 12-Bit, 105Msps Low Power 3V ADC
LTC2282IUP-TR 制造商:LINER 制造商全稱:Linear Technology 功能描述:Dual 12-Bit, 105Msps Low Power 3V ADC
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*