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參數(shù)資料
| 型號： | LTC2284IUP#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 10/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC DUAL 14BIT 105MSPS 64-QFN |
| 標準包裝： | 2,000 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 105M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 630mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-WFQFN 裸露焊盤 |
| 供應商設(shè)備封裝： | 64-QFN（9x9） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個單端，雙極; 2 個差分, 雙極 |
LTC2284
2284fa
18
Data Format
Using the MODE pin, the LTC2284 parallel digital output
can be selected for offset binary or 2’s complement
format. Connecting MODE to GND or 1/3VDD selects
offset binary output format. Connecting MODE to 2/3VDD
or VDD selects 2’s complement output format. An external
resistor divider can be used to set the 1/3VDD or 2/3VDD
logic values. Table 2 shows the logic states for the MODE
pin.
Sleep and Nap Modes
The converter may be placed in shutdown or nap modes
to conserve power. Connecting SHDN to GND results in
normal operation. Connecting SHDN to VDD and OE to VDD
results in sleep mode, which powers down all circuitry
including the reference and typically dissipates 1mW. When
exiting sleep mode it will take milliseconds for the output
data to become valid because the reference capacitors have
to recharge and stabilize. Connecting SHDN to VDD and OE
to GND results in nap mode, which typically dissipates
30mW. In nap mode, the on-chip reference circuit is kept
on, so that recovery from nap mode is faster than that from
sleep mode, typically taking 100 clock cycles. In both sleep
and nap modes, all digital outputs are disabled and enter
the Hi-Z state.
SHDNB). Channel A is controlled by SHDNA and OEA, and
Channel B is controlled by SHDNB and OEB. The nap, sleep
and output enable modes of the two channels are completely
independent, so it is possible to have one channel operat-
ing while the other channel is in nap or sleep mode.
Digital Output Multiplexer
The digital outputs of the LTC2284 can be multiplexed onto
a single data bus if the sample rate is 80Msps or less. The
MUX pin is a digital input that swaps the two data busses.
If MUX is High, Channel A comes out on DA0-DA13, OFA;
Channel B comes out on DB0-DB13, OFB. If MUX is Low,
the output busses are swapped and Channel A comes out
on DB0-DB13, OFB; Channel B comes out on DA0-DA13,
OFA. To multiplex both channels onto a single output bus,
connect MUX, CLKA and CLKB together (see the Timing
Diagram for the multiplexed mode). The multiplexed data
is available on either data bus—the unused data bus can
be disabled with its OE pin.
Table 2. MODE Pin Function
Clock Duty
MODE Pin
Output Format
Cycle Stabilizer
0
Offset Binary
Off
1/3VDD
Offset Binary
On
2/3VDD
2’s Complement
On
VDD
2’s Complement
Off
APPLICATIO S I FOR ATIO
WU
U
Overflow Bit
When OF outputs a logic high the converter is either
overranged or underranged.
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OVDD, should be tied
to the same power supply as for the logic being driven. For
example, if the converter is driving a DSP powered by a 1.8V
supply, then OVDD should be tied to that same 1.8V supply.
OVDD can be powered with any voltage from 500mV up to
3.6V. OGND can be powered with any voltage from GND up
to 1V and must be less than OVDD. The logic outputs will
swing between OGND and OVDD.
Output Enable
The outputs may be disabled with the output enable pin, OE.
OE high disables all data outputs including OF. The data ac-
cess and bus relinquish times are too slow to allow the
outputs to be enabled and disabled during full speed op-
eration. The output Hi-Z state is intended for use during long
periods of inactivity. Channels A and B have independent
output enable pins (OEA, OEB).
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