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參數資料
| 型號： | LTC2294IUP#PBF |
| 廠商： | Linear Technology |
| 文件頁數： | 24/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC DUAL 12BIT 80MSPS 64QFN |
| 標準包裝： | 40 |
| 位數： | 12 |
| 采樣率（每秒）： | 80M |
| 數據接口： | 并聯(lián) |
| 轉換器數目： | 2 |
| 功率耗散（最大）： | 495mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-WFQFN 裸露焊盤 |
| 供應商設備封裝： | 64-QFN（9x9） |
| 包裝： | 管件 |
| 輸入數目和類型： | 2 個單端，雙極; 2 個差分, 雙極 |
| 產品目錄頁面： | 1349 (CN2011-ZH PDF) |
LTC2294
9
2294fa
SHDNA (Pin 59): Channel A Shutdown Mode Selection
Pin. Connecting SHDNA to GND and OEA to GND results
in normal operation with the outputs enabled. Connecting
SHDNA to GND and OEA to VDD results in normal opera-
tion with the outputs at high impedance. Connecting
SHDNA to VDD and OEA to GND results in nap mode with
the outputs at high impedance. Connecting SHDNA to VDD
and OEA to VDD results in sleep mode with the outputs at
high impedance.
MODE (Pin 60): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Note that MODE controls both
channels. Connecting MODE to GND selects offset binary
output format and turns the clock duty cycle stabilizer off.
1/3 VDD selects offset binary output format and turns the
clock duty cycle stabilizer on. 2/3 VDD selects 2’s comple-
ment output format and turns the clock duty cycle stabi-
UU
U
PI FU CTIO S
lizer on. VDD selects 2’s complement output format and
turns the clock duty cycle stabilizer off.
VCMA (Pin 61): Channel A 1.5V Output and Input Common
Mode Bias. Bypass to ground with 2.2
F ceramic chip
capacitor. Do not connect to VCMB.
SENSEA (Pin 62): Channel A Reference Programming Pin.
Connecting SENSEA to VCMA selects the internal reference
and a
±0.5V input range. VDD selects the internal reference
and a
±1V input range. An external reference greater than
0.5V and less than 1V applied to SENSEA selects an input
range of
±VSENSEA. ±1V is the largest valid input range.
GND (Exposed Pad) (Pin 65): ADC Power Ground. The
Exposed Pad on the bottom of the package needs to be
soldered to ground.
FUNCTIONAL BLOCK DIAGRA
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Figure 1. Functional Block Diagram (Only One Channel is Shown)
SHIFT REGISTER
AND CORRECTION
DIFF
REF
AMP
REF
BUF
2.2
F
1
F1F
0.1
F
INTERNAL CLOCK SIGNALS
REFH
REFL
CLOCK/DUTY
CYCLE
CONTROL
RANGE
SELECT
1.5V
REFERENCE
FIRST PIPELINED
ADC STAGE
FIFTH PIPELINED
ADC STAGE
SIXTH PIPELINED
ADC STAGE
FOURTH PIPELINED
ADC STAGE
SECOND PIPELINED
ADC STAGE
REFH
REFL
CLK
OE
MODE
OGND
OVDD
2294 F01
INPUT
S/H
SENSE
VCM
AIN
–
AIN
+
2.2
F
THIRD PIPELINED
ADC STAGE
OUTPUT
DRIVERS
CONTROL
LOGIC
SHDN
OF
D11
D0
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相關代理商/技術參數 |
參數描述 |
|---|---|
| LTC2294UP | 制造商:LINER 制造商全稱:Linear Technology 功能描述:Dual 12-Bit, 80Msps Low Power 3V ADC |
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| LTC2295CUP | 制造商:Linear Technology 功能描述:ADC Dual Pipelined 10Msps 14-bit Parallel 64-Pin QFN EP |
| LTC2295CUP#PBF | 功能描述:IC ADC DUAL 14BIT 10MSPS 64QFN RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 標準包裝:1 系列:- 位數:14 采樣率（每秒）:83k 數據接口:串行，并聯(lián) 轉換器數目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應商設備封裝:28-PDIP 包裝:管件 輸入數目和類型:1 個單端，雙極 |
| LTC2295CUP#TRPBF | 功能描述:IC ADC DUAL 14BIT 10MSPS 64QFN RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 標準包裝:1 系列:- 位數:14 采樣率（每秒）:83k 數據接口:串行，并聯(lián) 轉換器數目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應商設備封裝:28-PDIP 包裝:管件 輸入數目和類型:1 個單端，雙極 |
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